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numam-dpdk/lib/librte_ring/Makefile

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lib: use SPDX tag for Intel copyright files Replace the BSD license header with the SPDX tag for files with only an Intel copyright on them. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2017-12-19 15:49:03 +00:00
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2010-2014 Intel Corporation
first public release version 1.2.3 Signed-off-by: Intel
2012-09-04 12:54:00 +00:00
include $(RTE_SDK)/mk/rte.vars.mk
# library name
LIB = librte_ring.a
CFLAGS += $(WERROR_FLAGS) -I$(SRCDIR) -O3
mk: do not generate LDLIBS from directory dependencies The list of libraries in LDLIBS was generated from the DEPDIRS-xyz variable. This is valid when the subdirectory name match the library name, but it's not always the case, especially for PMDs. The patches removes this feature and explicitly adds the proper libraries in LDLIBS. Some DEPDIRS-xyz variables become useless, remove them. Reported-by: Gage Eads <gage.eads@intel.com> Signed-off-by: Olivier Matz <olivier.matz@6wind.com> Reviewed-by: Gage Eads <gage.eads@intel.com>
2017-10-12 16:04:21 +00:00
LDLIBS += -lrte_eal
first public release version 1.2.3 Signed-off-by: Intel
2012-09-04 12:54:00 +00:00
lib: provide initial versioning Add linker version script files to each DPDK library to put a stake in the ground from which we can start cleaning up API's Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
2015-02-02 17:40:20 +00:00
EXPORT_MAP := rte_ring_version.map
ring: relax alignment constraint on ring structure The initial objective of commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting") was to add an empty cache line between the producer and consumer data (on platform with cache line size = 64B), preventing from having them on adjacent cache lines. Following discussion on the mailing list, it appears that this also imposes an alignment constraint that is not required. This patch removes the extra alignment constraint and adds the empty cache lines using padding fields in the structure. The size of rte_ring structure and the offset of the fields remain the same on platforms with cache line size = 64B: rte_ring = 384 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 rte_ring.cons = 256 But it has an impact on platform where cache line size is 128B: rte_ring = 384 -> 768 rte_ring.name = 0 rte_ring.flags = 32 rte_ring.memzone = 40 rte_ring.size = 48 rte_ring.mask = 52 rte_ring.prod = 128 -> 256 rte_ring.cons = 256 -> 512 Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
2018-04-03 13:26:44 +00:00
LIBABIVER := 2
mk: add library version extension To differentiate libraries that break ABI, we add a library version number suffix to the library, which must be incremented when a given libraries ABI is broken. This patch enforces that addition, sets the initial abi soname extension to 1 for each library and creates a symlink to the base SONAME so that the test applications will link properly. Signed-off-by: Neil Horman <nhorman@tuxdriver.com> Acked-by: Sergio Gonzalez Monroy <sergio.gonzalez.monroy@intel.com>
2015-02-02 17:40:21 +00:00
first public release version 1.2.3 Signed-off-by: Intel
2012-09-04 12:54:00 +00:00
# all source are stored in SRCS-y
SRCS-$(CONFIG_RTE_LIBRTE_RING) := rte_ring.c
# install includes
ring: move code in a new header file Move the common part of rte_ring.h into rte_ring_generic.h. Move the memory barrier part into update_tail(). No functional changes here. Suggested-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Signed-off-by: Jia He <jia.he@hxt-semitech.com> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Olivier Matz <olivier.matz@6wind.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2018-01-22 04:41:27 +00:00
SYMLINK-$(CONFIG_RTE_LIBRTE_RING)-include := rte_ring.h \
ring: introduce C11 memory model barrier option This patch is to support C11 memory model barrier in librte_ring. There are 2 barrier implementation options in librte_ring (suggested by Jerin). 1. use rte_smp_rmb 2. use load_acquire/store_release(refer to [1]). The reason why providing 2 options is the performance benchmark difference in different arm machines, refer to [2]. CONFIG_RTE_RING_USE_C11_MEM_MODEL is provided, and by default it is "n" on any architectures and only "y" on arm64 so far. [1] https://github.com/freebsd/freebsd/blob/master/sys/sys/buf_ring.h#L170 [2] http://dpdk.org/ml/archives/dev/2017-October/080861.html Suggested-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Signed-off-by: Jia He <jia.he@hxt-semitech.com> Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Olivier Matz <olivier.matz@6wind.com> Acked-by: Jianbo Liu <jianbo.liu@arm.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2018-01-22 04:41:28 +00:00
rte_ring_generic.h \
rte_ring_c11_mem.h
first public release version 1.2.3 Signed-off-by: Intel
2012-09-04 12:54:00 +00:00
include $(RTE_SDK)/mk/rte.lib.mk
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