2018-01-29 13:11:30 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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2018-03-20 19:20:35 +00:00
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* Copyright 2015 Mellanox Technologies, Ltd
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2015-10-30 18:52:30 +00:00
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*/
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#ifndef RTE_PMD_MLX5_DEFS_H_
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#define RTE_PMD_MLX5_DEFS_H_
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2018-01-22 00:16:22 +00:00
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#include <rte_ethdev_driver.h>
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2019-10-23 13:19:27 +00:00
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#include <rte_vxlan.h>
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2018-01-03 09:14:19 +00:00
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2016-03-03 14:26:43 +00:00
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#include "mlx5_autoconf.h"
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2015-10-30 18:52:30 +00:00
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/* Reported driver name. */
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2016-10-07 13:04:13 +00:00
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#define MLX5_DRIVER_NAME "net_mlx5"
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2015-10-30 18:52:30 +00:00
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2018-04-23 11:09:27 +00:00
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/* Maximum number of simultaneous unicast MAC addresses. */
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#define MLX5_MAX_UC_MAC_ADDRESSES 128
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2018-04-23 11:09:28 +00:00
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/* Maximum number of simultaneous Multicast MAC addresses. */
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#define MLX5_MAX_MC_MAC_ADDRESSES 128
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2015-10-30 18:52:30 +00:00
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/* Maximum number of simultaneous MAC addresses. */
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2018-04-23 11:09:28 +00:00
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#define MLX5_MAX_MAC_ADDRESSES \
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(MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
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2015-10-30 18:52:30 +00:00
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2015-10-30 18:52:40 +00:00
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/* Maximum number of simultaneous VLAN filters. */
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#define MLX5_MAX_VLAN_IDS 128
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2016-06-24 13:17:55 +00:00
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/*
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* Request TX completion every time descriptors reach this threshold since
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* the previous request. Must be a power of two for performance reasons.
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*/
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2019-07-29 12:41:05 +00:00
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#define MLX5_TX_COMP_THRESH 32u
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2015-10-30 18:52:31 +00:00
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2017-03-15 23:55:44 +00:00
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/*
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* Request TX completion every time the total number of WQEBBs used for inlining
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* packets exceeds the size of WQ divided by this divisor. Better to be power of
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* two for performance.
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*/
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#define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3)
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2019-07-29 12:41:03 +00:00
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/*
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* Maximal amount of normal completion CQEs
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* processed in one call of tx_burst() routine.
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*/
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#define MLX5_TX_COMP_MAX_CQE 2u
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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/* Size of per-queue MR cache array for linear search. */
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#define MLX5_MR_CACHE_N 8
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/* Size of MR cache table for binary search. */
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#define MLX5_MR_BTREE_CACHE_N 256
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2015-10-30 18:52:36 +00:00
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/*
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* If defined, only use software counters. The PMD will never ask the hardware
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* for these, and many of them won't be available.
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*/
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#ifndef MLX5_PMD_SOFT_COUNTERS
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#define MLX5_PMD_SOFT_COUNTERS 1
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#endif
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2019-09-25 07:53:34 +00:00
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/* Switch port ID parameters for bonding configurations. */
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#define MLX5_PORT_ID_BONDING_PF_MASK 0xf
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#define MLX5_PORT_ID_BONDING_PF_SHIFT 0xf
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2015-10-30 18:57:23 +00:00
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/* Alarm timeout. */
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#define MLX5_ALARM_TIMEOUT_US 100000
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2017-01-17 14:37:08 +00:00
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/* Maximum number of extended statistics counters. */
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#define MLX5_MAX_XSTATS 32
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2017-03-02 09:01:31 +00:00
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/* Maximum Packet headers size (L2+L3+L4) for TSO. */
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2019-07-21 14:24:55 +00:00
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#define MLX5_MAX_TSO_HEADER (128u + 34u)
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2017-03-02 09:01:31 +00:00
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2019-07-21 14:24:56 +00:00
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/* Inline data size required by NICs. */
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#define MLX5_INLINE_HSIZE_NONE 0
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#define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_vlan_hdr))
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#define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \
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sizeof(struct rte_ipv6_hdr))
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#define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \
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sizeof(struct rte_tcp_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \
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sizeof(struct rte_udp_hdr) + \
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sizeof(struct rte_vxlan_hdr) + \
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sizeof(struct rte_ether_hdr) + \
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sizeof(struct rte_vlan_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \
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sizeof(struct rte_ipv6_hdr))
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#define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \
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sizeof(struct rte_tcp_hdr))
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2017-07-06 18:41:10 +00:00
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/* Threshold of buffer replenishment for vectorized Rx. */
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2018-06-26 11:33:35 +00:00
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#define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \
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(RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2))
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2017-07-06 18:41:10 +00:00
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/* Maximum size of burst for vectorized Rx. */
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2018-06-26 11:33:35 +00:00
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#define MLX5_VPMD_RX_MAX_BURST 64U
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2017-07-06 18:41:10 +00:00
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/* Number of packets vectorized Rx can simultaneously process in a loop. */
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#define MLX5_VPMD_DESCS_PER_LOOP 4
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2018-01-03 09:14:19 +00:00
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/* Supported RSS */
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#define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP))
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2018-03-12 13:43:19 +00:00
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/* Timeout in seconds to get a valid link status. */
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#define MLX5_LINK_STATUS_TIMEOUT 10
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2018-01-25 16:04:28 +00:00
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2019-10-16 07:34:03 +00:00
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/* Number of times to retry retrieving the physical link information. */
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#define MLX5_GET_LINK_STATUS_RETRY_COUNT 3
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2018-07-12 12:01:31 +00:00
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/* Maximum number of UAR pages used by a port,
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* These are the size and mask for an array of mutexes used to synchronize
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* the access to port's UARs on platforms that do not support 64 bit writes.
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* In such systems it is possible to issue the 64 bits DoorBells through two
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* consecutive writes, each write 32 bits. The access to a UAR page (which can
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* be accessible by all threads in the process) must be synchronized
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* (for example, using a semaphore). Such a synchronization is not required
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* when ringing DoorBells on different UAR pages.
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* A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared
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* among the ports.
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*/
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#define MLX5_UAR_PAGE_NUM_MAX 64
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#define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1)
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2018-01-25 15:00:24 +00:00
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2018-05-09 11:13:50 +00:00
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/* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */
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2018-06-26 12:39:25 +00:00
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#define MLX5_MPRQ_STRIDE_NUM_N 6U
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2018-05-09 11:13:50 +00:00
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/* Two-byte shift is disabled for Multi-Packet RQ. */
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#define MLX5_MPRQ_TWO_BYTE_SHIFT 0
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/*
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* Minimum size of packet to be memcpy'd instead of being attached as an
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* external buffer.
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*/
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#define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128
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/* Minimum number Rx queues to enable Multi-Packet RQ. */
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#define MLX5_MPRQ_MIN_RXQS 12
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/* Cache size of mempool for Multi-Packet RQ. */
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2018-08-02 21:00:07 +00:00
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#define MLX5_MPRQ_MP_CACHE_SZ 32U
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2018-05-09 11:13:50 +00:00
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2018-07-15 17:31:39 +00:00
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/* Definition of static_assert found in /usr/include/assert.h */
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#ifndef HAVE_STATIC_ASSERT
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#define static_assert _Static_assert
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#endif
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2015-10-30 18:52:30 +00:00
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#endif /* RTE_PMD_MLX5_DEFS_H_ */
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