2015-10-30 18:52:30 +00:00
|
|
|
/*-
|
|
|
|
|
* BSD LICENSE
|
|
|
|
|
*
|
|
|
|
|
* Copyright 2015 6WIND S.A.
|
|
|
|
|
* Copyright 2015 Mellanox.
|
|
|
|
|
*
|
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
|
* are met:
|
|
|
|
|
*
|
|
|
|
|
* * Redistributions of source code must retain the above copyright
|
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
|
|
|
* notice, this list of conditions and the following disclaimer in
|
|
|
|
|
* the documentation and/or other materials provided with the
|
|
|
|
|
* distribution.
|
|
|
|
|
* * Neither the name of 6WIND S.A. nor the names of its
|
|
|
|
|
* contributors may be used to endorse or promote products derived
|
|
|
|
|
* from this software without specific prior written permission.
|
|
|
|
|
*
|
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef RTE_PMD_MLX5_H_
|
|
|
|
|
#define RTE_PMD_MLX5_H_
|
|
|
|
|
|
|
|
|
|
#include <stddef.h>
|
|
|
|
|
#include <stdint.h>
|
|
|
|
|
#include <limits.h>
|
|
|
|
|
#include <net/if.h>
|
|
|
|
|
#include <netinet/in.h>
|
2017-10-09 14:44:53 +00:00
|
|
|
#include <sys/queue.h>
|
2015-10-30 18:52:30 +00:00
|
|
|
|
|
|
|
|
/* Verbs header. */
|
|
|
|
|
/* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
|
|
|
|
|
#ifdef PEDANTIC
|
2016-09-19 14:36:54 +00:00
|
|
|
#pragma GCC diagnostic ignored "-Wpedantic"
|
2015-10-30 18:52:30 +00:00
|
|
|
#endif
|
|
|
|
|
#include <infiniband/verbs.h>
|
|
|
|
|
#ifdef PEDANTIC
|
2016-09-19 14:36:54 +00:00
|
|
|
#pragma GCC diagnostic error "-Wpedantic"
|
2015-10-30 18:52:30 +00:00
|
|
|
#endif
|
|
|
|
|
|
2017-07-07 00:04:20 +00:00
|
|
|
#include <rte_pci.h>
|
2015-10-30 18:52:30 +00:00
|
|
|
#include <rte_ether.h>
|
|
|
|
|
#include <rte_ethdev.h>
|
|
|
|
|
#include <rte_spinlock.h>
|
2015-10-30 18:57:23 +00:00
|
|
|
#include <rte_interrupts.h>
|
2016-03-17 15:38:55 +00:00
|
|
|
#include <rte_errno.h>
|
2016-12-29 15:15:17 +00:00
|
|
|
#include <rte_flow.h>
|
2015-10-30 18:52:30 +00:00
|
|
|
|
|
|
|
|
#include "mlx5_utils.h"
|
2015-10-30 18:52:31 +00:00
|
|
|
#include "mlx5_rxtx.h"
|
2015-10-30 18:52:30 +00:00
|
|
|
#include "mlx5_autoconf.h"
|
|
|
|
|
#include "mlx5_defs.h"
|
|
|
|
|
|
|
|
|
|
enum {
|
|
|
|
|
PCI_VENDOR_ID_MELLANOX = 0x15b3,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum {
|
|
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
|
|
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
|
|
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
|
|
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
|
2017-01-06 00:49:31 +00:00
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
|
|
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
|
|
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
|
|
|
|
|
PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
|
2015-10-30 18:52:30 +00:00
|
|
|
};
|
|
|
|
|
|
2017-01-17 14:37:08 +00:00
|
|
|
struct mlx5_xstats_ctrl {
|
|
|
|
|
/* Number of device stats. */
|
|
|
|
|
uint16_t stats_n;
|
|
|
|
|
/* Index in the device counters table. */
|
|
|
|
|
uint16_t dev_table_idx[MLX5_MAX_XSTATS];
|
|
|
|
|
uint64_t base[MLX5_MAX_XSTATS];
|
|
|
|
|
};
|
|
|
|
|
|
2017-10-09 14:44:53 +00:00
|
|
|
/* Flow list . */
|
|
|
|
|
TAILQ_HEAD(mlx5_flows, rte_flow);
|
|
|
|
|
|
2018-01-10 09:16:58 +00:00
|
|
|
/* Default PMD specific parameter value. */
|
|
|
|
|
#define MLX5_ARG_UNSET (-1)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Device configuration structure.
|
|
|
|
|
*
|
|
|
|
|
* Merged configuration from:
|
|
|
|
|
*
|
|
|
|
|
* - Device capabilities,
|
|
|
|
|
* - User device parameters disabled features.
|
|
|
|
|
*/
|
|
|
|
|
struct mlx5_dev_config {
|
|
|
|
|
unsigned int hw_csum:1; /* Checksum offload is supported. */
|
|
|
|
|
unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
|
|
|
|
|
unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
|
|
|
|
|
unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
|
|
|
|
|
unsigned int hw_padding:1; /* End alignment padding is supported. */
|
|
|
|
|
unsigned int sriov:1; /* This is a VF or PF with VF devices. */
|
|
|
|
|
unsigned int mps:2; /* Multi-packet send supported mode. */
|
|
|
|
|
unsigned int tunnel_en:1; /* Whether tunnel is supported. */
|
2018-01-10 09:16:59 +00:00
|
|
|
unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
|
2018-01-10 09:16:58 +00:00
|
|
|
unsigned int cqe_comp:1; /* CQE compression is enabled. */
|
|
|
|
|
unsigned int tso:1; /* Whether TSO is enabled. */
|
|
|
|
|
unsigned int tx_vec_en:1; /* Tx vector is enabled. */
|
|
|
|
|
unsigned int rx_vec_en:1; /* Rx vector is enabled. */
|
|
|
|
|
unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
|
|
|
|
|
unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
|
|
|
|
|
unsigned int ind_table_max_size; /* Maximum indirection table size. */
|
|
|
|
|
int txq_inline; /* Maximum packet size for inlining. */
|
|
|
|
|
int txqs_inline; /* Queue number threshold for inlining. */
|
|
|
|
|
int inline_max_packet_sz; /* Max packet size for inlining. */
|
|
|
|
|
};
|
|
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
struct priv {
|
2017-10-06 15:45:48 +00:00
|
|
|
struct rte_eth_dev *dev; /* Ethernet device of master process. */
|
2015-10-30 18:52:30 +00:00
|
|
|
struct ibv_context *ctx; /* Verbs context. */
|
2017-09-26 15:38:24 +00:00
|
|
|
struct ibv_device_attr_ex device_attr; /* Device properties. */
|
2015-10-30 18:52:30 +00:00
|
|
|
struct ibv_pd *pd; /* Protection Domain. */
|
2017-10-06 15:45:51 +00:00
|
|
|
char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
|
2017-10-09 14:44:55 +00:00
|
|
|
struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
|
2015-10-30 18:52:40 +00:00
|
|
|
uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
|
|
|
|
|
unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
|
2015-10-30 18:52:30 +00:00
|
|
|
/* Device properties. */
|
|
|
|
|
uint16_t mtu; /* Configured MTU. */
|
|
|
|
|
uint8_t port; /* Physical port number. */
|
2015-10-30 18:57:23 +00:00
|
|
|
unsigned int pending_alarm:1; /* An alarm is pending. */
|
2017-05-24 13:44:08 +00:00
|
|
|
unsigned int isolated:1; /* Whether isolated mode is enabled. */
|
2015-10-30 18:52:31 +00:00
|
|
|
/* RX/TX queues. */
|
|
|
|
|
unsigned int rxqs_n; /* RX queues array size. */
|
|
|
|
|
unsigned int txqs_n; /* TX queues array size. */
|
2017-10-09 14:44:39 +00:00
|
|
|
struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
|
2017-10-09 14:44:40 +00:00
|
|
|
struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
|
2015-10-30 18:55:08 +00:00
|
|
|
unsigned int ind_table_max_size; /* Maximum indirection table size. */
|
2017-10-09 14:44:56 +00:00
|
|
|
struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
|
2015-10-30 18:57:23 +00:00
|
|
|
struct rte_intr_handle intr_handle; /* Interrupt handler. */
|
2015-11-02 18:11:57 +00:00
|
|
|
unsigned int (*reta_idx)[]; /* RETA index table. */
|
|
|
|
|
unsigned int reta_idx_n; /* RETA index size. */
|
2017-10-09 14:44:51 +00:00
|
|
|
struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */
|
2017-10-09 14:44:53 +00:00
|
|
|
struct mlx5_flows flows; /* RTE Flow rules. */
|
|
|
|
|
struct mlx5_flows ctrl_flows; /* Control flow rules. */
|
2017-10-09 14:44:45 +00:00
|
|
|
LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */
|
2017-10-09 14:44:49 +00:00
|
|
|
LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
|
2017-10-09 14:44:46 +00:00
|
|
|
LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
|
2017-10-09 14:44:51 +00:00
|
|
|
LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
|
2017-10-09 14:44:48 +00:00
|
|
|
LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
|
2017-10-09 14:44:47 +00:00
|
|
|
LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
|
2017-10-09 14:44:50 +00:00
|
|
|
/* Verbs Indirection tables. */
|
|
|
|
|
LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
|
2016-10-26 09:44:01 +00:00
|
|
|
uint32_t link_speed_capa; /* Link speed capabilities. */
|
2017-01-17 14:37:08 +00:00
|
|
|
struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
|
2015-10-30 18:52:30 +00:00
|
|
|
rte_spinlock_t lock; /* Lock for control functions. */
|
2017-10-06 15:45:49 +00:00
|
|
|
int primary_socket; /* Unix socket for primary process. */
|
|
|
|
|
struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
|
2018-01-10 09:16:58 +00:00
|
|
|
struct mlx5_dev_config config; /* Device configuration. */
|
2015-10-30 18:52:30 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Lock private structure to protect it from concurrent access in the
|
|
|
|
|
* control path.
|
|
|
|
|
*
|
|
|
|
|
* @param priv
|
|
|
|
|
* Pointer to private structure.
|
|
|
|
|
*/
|
|
|
|
|
static inline void
|
|
|
|
|
priv_lock(struct priv *priv)
|
|
|
|
|
{
|
|
|
|
|
rte_spinlock_lock(&priv->lock);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Unlock private structure.
|
|
|
|
|
*
|
|
|
|
|
* @param priv
|
|
|
|
|
* Pointer to private structure.
|
|
|
|
|
*/
|
|
|
|
|
static inline void
|
|
|
|
|
priv_unlock(struct priv *priv)
|
|
|
|
|
{
|
|
|
|
|
rte_spinlock_unlock(&priv->lock);
|
|
|
|
|
}
|
|
|
|
|
|
2016-03-17 15:38:57 +00:00
|
|
|
/* mlx5.c */
|
|
|
|
|
|
|
|
|
|
int mlx5_getenv_int(const char *);
|
|
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
/* mlx5_ethdev.c */
|
|
|
|
|
|
2016-03-17 15:38:55 +00:00
|
|
|
struct priv *mlx5_get_priv(struct rte_eth_dev *dev);
|
|
|
|
|
int mlx5_is_secondary(void);
|
2015-10-30 18:52:30 +00:00
|
|
|
int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]);
|
|
|
|
|
int priv_ifreq(const struct priv *, int req, struct ifreq *);
|
2017-02-14 14:31:06 +00:00
|
|
|
int priv_is_ib_cntr(const char *);
|
|
|
|
|
int priv_get_cntr_sysfs(struct priv *, const char *, uint64_t *);
|
2016-06-08 09:43:30 +00:00
|
|
|
int priv_get_num_vfs(struct priv *, uint16_t *);
|
2015-10-30 18:52:30 +00:00
|
|
|
int priv_get_mtu(struct priv *, uint16_t *);
|
|
|
|
|
int priv_set_flags(struct priv *, unsigned int, unsigned int);
|
2015-10-30 18:52:33 +00:00
|
|
|
int mlx5_dev_configure(struct rte_eth_dev *);
|
|
|
|
|
void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *);
|
2016-03-14 20:50:50 +00:00
|
|
|
const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
|
2015-10-30 18:52:38 +00:00
|
|
|
int mlx5_link_update(struct rte_eth_dev *, int);
|
2015-10-30 18:52:35 +00:00
|
|
|
int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t);
|
2015-10-30 18:52:39 +00:00
|
|
|
int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
|
|
|
|
|
int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *);
|
2015-10-30 18:52:30 +00:00
|
|
|
int mlx5_ibv_device_to_pci_addr(const struct ibv_device *,
|
|
|
|
|
struct rte_pci_addr *);
|
2015-10-30 18:57:23 +00:00
|
|
|
void mlx5_dev_link_status_handler(void *);
|
2017-04-06 12:42:22 +00:00
|
|
|
void mlx5_dev_interrupt_handler(void *);
|
2015-10-30 18:57:23 +00:00
|
|
|
void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *);
|
|
|
|
|
void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *);
|
2016-03-17 15:38:54 +00:00
|
|
|
int mlx5_set_link_down(struct rte_eth_dev *dev);
|
|
|
|
|
int mlx5_set_link_up(struct rte_eth_dev *dev);
|
2018-01-10 09:16:57 +00:00
|
|
|
eth_tx_burst_t priv_select_tx_function(struct priv *, struct rte_eth_dev *);
|
|
|
|
|
eth_rx_burst_t priv_select_rx_function(struct priv *, struct rte_eth_dev *);
|
2015-10-30 18:52:30 +00:00
|
|
|
|
|
|
|
|
/* mlx5_mac.c */
|
|
|
|
|
|
|
|
|
|
int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]);
|
2015-10-30 18:52:32 +00:00
|
|
|
void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t);
|
2017-05-05 00:40:00 +00:00
|
|
|
int mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t,
|
|
|
|
|
uint32_t);
|
2016-01-05 18:00:09 +00:00
|
|
|
void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *);
|
2015-10-30 18:52:30 +00:00
|
|
|
|
2015-10-30 18:55:11 +00:00
|
|
|
/* mlx5_rss.c */
|
|
|
|
|
|
|
|
|
|
int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *);
|
|
|
|
|
int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *);
|
2015-11-02 18:11:57 +00:00
|
|
|
int priv_rss_reta_index_resize(struct priv *, unsigned int);
|
|
|
|
|
int mlx5_dev_rss_reta_query(struct rte_eth_dev *,
|
|
|
|
|
struct rte_eth_rss_reta_entry64 *, uint16_t);
|
|
|
|
|
int mlx5_dev_rss_reta_update(struct rte_eth_dev *,
|
|
|
|
|
struct rte_eth_rss_reta_entry64 *, uint16_t);
|
2015-10-30 18:55:11 +00:00
|
|
|
|
2015-10-30 18:52:37 +00:00
|
|
|
/* mlx5_rxmode.c */
|
|
|
|
|
|
|
|
|
|
void mlx5_promiscuous_enable(struct rte_eth_dev *);
|
|
|
|
|
void mlx5_promiscuous_disable(struct rte_eth_dev *);
|
|
|
|
|
void mlx5_allmulticast_enable(struct rte_eth_dev *);
|
|
|
|
|
void mlx5_allmulticast_disable(struct rte_eth_dev *);
|
|
|
|
|
|
2015-10-30 18:52:36 +00:00
|
|
|
/* mlx5_stats.c */
|
|
|
|
|
|
2017-01-17 14:37:08 +00:00
|
|
|
void priv_xstats_init(struct priv *);
|
2017-10-10 20:20:18 +00:00
|
|
|
int mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *);
|
2015-10-30 18:52:36 +00:00
|
|
|
void mlx5_stats_reset(struct rte_eth_dev *);
|
2017-01-17 14:37:08 +00:00
|
|
|
int mlx5_xstats_get(struct rte_eth_dev *,
|
|
|
|
|
struct rte_eth_xstat *, unsigned int);
|
|
|
|
|
void mlx5_xstats_reset(struct rte_eth_dev *);
|
|
|
|
|
int mlx5_xstats_get_names(struct rte_eth_dev *,
|
|
|
|
|
struct rte_eth_xstat_name *, unsigned int);
|
2015-10-30 18:52:36 +00:00
|
|
|
|
2015-10-30 18:52:40 +00:00
|
|
|
/* mlx5_vlan.c */
|
|
|
|
|
|
|
|
|
|
int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int);
|
2017-09-01 02:36:28 +00:00
|
|
|
int mlx5_vlan_offload_set(struct rte_eth_dev *, int);
|
2016-03-03 14:26:44 +00:00
|
|
|
void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int);
|
2015-10-30 18:52:40 +00:00
|
|
|
|
2015-10-30 18:52:33 +00:00
|
|
|
/* mlx5_trigger.c */
|
|
|
|
|
|
|
|
|
|
int mlx5_dev_start(struct rte_eth_dev *);
|
|
|
|
|
void mlx5_dev_stop(struct rte_eth_dev *);
|
2017-10-09 14:44:55 +00:00
|
|
|
int priv_dev_traffic_enable(struct priv *, struct rte_eth_dev *);
|
|
|
|
|
int priv_dev_traffic_disable(struct priv *, struct rte_eth_dev *);
|
|
|
|
|
int priv_dev_traffic_restart(struct priv *, struct rte_eth_dev *);
|
|
|
|
|
int mlx5_traffic_restart(struct rte_eth_dev *);
|
2015-10-30 18:52:33 +00:00
|
|
|
|
2017-10-09 14:44:38 +00:00
|
|
|
/* mlx5_flow.c */
|
2016-03-03 14:26:43 +00:00
|
|
|
|
|
|
|
|
int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type,
|
|
|
|
|
enum rte_filter_op, void *);
|
2016-12-29 15:15:17 +00:00
|
|
|
int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *,
|
|
|
|
|
const struct rte_flow_item [],
|
|
|
|
|
const struct rte_flow_action [],
|
|
|
|
|
struct rte_flow_error *);
|
|
|
|
|
struct rte_flow *mlx5_flow_create(struct rte_eth_dev *,
|
|
|
|
|
const struct rte_flow_attr *,
|
|
|
|
|
const struct rte_flow_item [],
|
|
|
|
|
const struct rte_flow_action [],
|
|
|
|
|
struct rte_flow_error *);
|
|
|
|
|
int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *,
|
|
|
|
|
struct rte_flow_error *);
|
2017-10-09 14:44:53 +00:00
|
|
|
void priv_flow_flush(struct priv *, struct mlx5_flows *);
|
2016-12-29 15:15:17 +00:00
|
|
|
int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *);
|
2017-10-10 14:22:54 +00:00
|
|
|
int mlx5_flow_query(struct rte_eth_dev *, struct rte_flow *,
|
|
|
|
|
enum rte_flow_action_type, void *,
|
|
|
|
|
struct rte_flow_error *);
|
2017-05-24 13:44:08 +00:00
|
|
|
int mlx5_flow_isolate(struct rte_eth_dev *, int, struct rte_flow_error *);
|
2017-10-09 14:44:53 +00:00
|
|
|
int priv_flow_start(struct priv *, struct mlx5_flows *);
|
|
|
|
|
void priv_flow_stop(struct priv *, struct mlx5_flows *);
|
2017-10-09 14:44:42 +00:00
|
|
|
int priv_flow_verify(struct priv *);
|
2017-10-09 14:44:55 +00:00
|
|
|
int mlx5_ctrl_flow_vlan(struct rte_eth_dev *, struct rte_flow_item_eth *,
|
|
|
|
|
struct rte_flow_item_eth *, struct rte_flow_item_vlan *,
|
|
|
|
|
struct rte_flow_item_vlan *);
|
2017-10-09 14:44:53 +00:00
|
|
|
int mlx5_ctrl_flow(struct rte_eth_dev *, struct rte_flow_item_eth *,
|
2017-10-09 14:44:55 +00:00
|
|
|
struct rte_flow_item_eth *);
|
|
|
|
|
int priv_flow_create_drop_queue(struct priv *);
|
|
|
|
|
void priv_flow_delete_drop_queue(struct priv *);
|
2016-12-29 15:15:17 +00:00
|
|
|
|
2017-10-06 15:45:49 +00:00
|
|
|
/* mlx5_socket.c */
|
|
|
|
|
|
|
|
|
|
int priv_socket_init(struct priv *priv);
|
|
|
|
|
int priv_socket_uninit(struct priv *priv);
|
|
|
|
|
void priv_socket_handle(struct priv *priv);
|
|
|
|
|
int priv_socket_connect(struct priv *priv);
|
|
|
|
|
|
2017-10-09 14:44:45 +00:00
|
|
|
/* mlx5_mr.c */
|
|
|
|
|
|
|
|
|
|
struct mlx5_mr *priv_mr_new(struct priv *, struct rte_mempool *);
|
|
|
|
|
struct mlx5_mr *priv_mr_get(struct priv *, struct rte_mempool *);
|
|
|
|
|
int priv_mr_release(struct priv *, struct mlx5_mr *);
|
|
|
|
|
int priv_mr_verify(struct priv *);
|
|
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
#endif /* RTE_PMD_MLX5_H_ */
|
