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version: 20.05-rc0 Start a new release cycle with empty release notes. ABI must now be checked with v20.02 as a reference. Signed-off-by: David Marchand <david.marchand@redhat.com> Acked-by: Thomas Monjalon <thomas@monjalon.net>
2020-02-25 16:32:00 +00:00
.. SPDX-License-Identifier: BSD-3-Clause
Copyright 2020 The DPDK contributors
.. include:: <isonum.txt>
DPDK Release 20.05
==================
.. **Read this first.**
The text in the sections below explains how to update the release notes.
Use proper spelling, capitalization and punctuation in all sections.
Variable and config names should be quoted as fixed width text:
``LIKE_THIS``.
Build the docs and view the output file to ensure the changes are correct::
make doc-guides-html
xdg-open build/doc/html/guides/rel_notes/release_20_05.html
New Features
------------
.. This section should contain new features added in this release.
Sample format:
* **Add a title in the past tense with a full stop.**
Add a short 1-2 sentence description in the past tense.
The description should be enough to allow someone scanning
the release notes to understand the new feature.
If the feature adds a lot of sub-features you can use a bullet list
like this:
* Added feature foo to do something.
* Enhanced feature bar to do something else.
Refer to the previous release notes for examples.
Suggested order in release notes items:
* Core libs (EAL, mempool, ring, mbuf, buses)
* Device abstraction libs and PMDs
- ethdev (lib, PMDs)
- cryptodev (lib, PMDs)
- eventdev (lib, PMDs)
- etc
* Other libs
* Apps, Examples, Tools (if significant)
This section is a comment. Do not overwrite or remove it.
Also, make sure to start the actual text at the margin.
=========================================================
doc: add trace library guide Add programmer's guide for trace library support. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Sunil Kumar Kori <skori@marvell.com> Acked-by: David Marchand <david.marchand@redhat.com>
2020-04-22 19:03:49 +00:00
* **Added Trace Library and Tracepoints**
A native implementation of ``common trace format(CTF)`` based trace library
has been added to provide the ability to add tracepoints in
application/library to get runtime trace/debug information for control and
fast APIs with minimum impact on fast path performance.
Typical trace overhead is ~20 cycles and instrumentation overhead is 1 cycle.
Added tracepoints in ``EAL``, ``ethdev``, ``cryptodev``, ``eventdev`` and
``mempool`` libraries for important functions.
ring: introduce peek style API For rings with producer/consumer in RTE_RING_SYNC_ST, RTE_RING_SYNC_MT_HTS mode, provide an ability to split enqueue/dequeue operation into two phases: - enqueue/dequeue start - enqueue/dequeue finish That allows user to inspect objects in the ring without removing them from it (aka MT safe peek). Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-20 12:28:28 +00:00
* **Added new API for rte_ring.**
* New synchronization modes for rte_ring.
ring: introduce RTS ring mode Introduce relaxed tail sync (RTS) mode for MT ring synchronization. Aim to reduce stall times in case when ring is used on overcommited cpus (multiple active threads on the same cpu). The main difference from original MP/MC algorithm is that tail value is increased not by every thread that finished enqueue/dequeue, but only by the last one. That allows threads to avoid spinning on ring tail value, leaving actual tail value change to the last thread in the update queue. Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-20 12:28:24 +00:00
ring: introduce HTS ring mode Introduce head/tail sync mode for MT ring synchronization. In that mode enqueue/dequeue operation is fully serialized: only one thread at a time is allowed to perform given op. Suppose to reduce stall times in case when ring is used on overcommitted cpus (multiple active threads on the same cpu). Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-20 12:28:26 +00:00
Introduced new optional MT synchronization modes for rte_ring:
Relaxed Tail Sync (RTS) mode and Head/Tail Sync (HTS) mode.
With these mode selected, rte_ring shows significant improvements for
average enqueue/dequeue times on overcommitted systems.
ring: introduce RTS ring mode Introduce relaxed tail sync (RTS) mode for MT ring synchronization. Aim to reduce stall times in case when ring is used on overcommited cpus (multiple active threads on the same cpu). The main difference from original MP/MC algorithm is that tail value is increased not by every thread that finished enqueue/dequeue, but only by the last one. That allows threads to avoid spinning on ring tail value, leaving actual tail value change to the last thread in the update queue. Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-20 12:28:24 +00:00
ring: introduce peek style API For rings with producer/consumer in RTE_RING_SYNC_ST, RTE_RING_SYNC_MT_HTS mode, provide an ability to split enqueue/dequeue operation into two phases: - enqueue/dequeue start - enqueue/dequeue finish That allows user to inspect objects in the ring without removing them from it (aka MT safe peek). Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-20 12:28:28 +00:00
* Added peek style API for rte_ring.
For rings with producer/consumer in RTE_RING_SYNC_ST, RTE_RING_SYNC_MT_HTS
mode, provide an ability to split enqueue/dequeue operation into two phases
(enqueue/dequeue start; enqueue/dequeue finish). That allows user to inspect
objects in the ring without removing them from it (aka MT safe peek).
ethdev: support flow aging One of the reasons to destroy a flow is the fact that no packet matches the flow for "timeout" time. For example, when TCP\UDP sessions are suddenly closed. Currently, there is not any DPDK mechanism for flow aging and the applications use their own ways to detect and destroy aged-out flows. The flow aging implementation need include: - A new rte_flow action: RTE_FLOW_ACTION_TYPE_AGE to set the timeout and the application flow context for each flow. - A new ethdev event: RTE_ETH_EVENT_FLOW_AGED for the driver to report that there are new aged-out flows. - A new rte_flow API: rte_flow_get_aged_flows to get the aged-out flows contexts from the port. - Support input flow aging command line in Testpmd. The new event type addition in the enum is flagged as an ABI breakage, so an ignore rule is added for these reasons: - It is not changing value of existing types (except MAX) - The new value is not used by existing API if the event is not registered In general, it is safe adding new ethdev event types at the end of the enum, because of event callback registration mechanism. Signed-off-by: Dong Zhou <dongz@mellanox.com> Acked-by: Ori Kam <orika@mellanox.com> Acked-by: Andrew Rybchenko <arybchenko@solarflare.com> Acked-by: Jerin Jacob <jerinj@marvell.com> Acked-by: Matan Azrad <matan@mellanox.com>
2020-04-21 10:11:38 +00:00
* **Added flow aging support.**
Added flow aging support to detect and report aged-out flows, including:
* Added new action: ``RTE_FLOW_ACTION_TYPE_AGE`` to set the timeout
and the application flow context for each flow.
* Added new event: ``RTE_ETH_EVENT_FLOW_AGED`` for the driver to report
that there are new aged-out flows.
* Added new query: ``rte_flow_get_aged_flows`` to get the aged-out flows
contexts from the port.
ethdev: add 200G link speed There is no way to report back a link speed of 200Gbps. Adding 200G link speed. Signed-off-by: Asaf Penso <asafp@mellanox.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-05-06 12:22:08 +00:00
* **ethdev: Added a new value to link speed for 200Gbps**
net/ena: support large LLQ headers Default LLQ (Low-latency queue) maximum header size is 96 bytes and can be too small for some types of packets - like IPv6 packets with multiple extension. This can be fixed, by using large LLQ headers. If the device supports larger LLQ headers, the user can activate them by using device argument 'large_llq_hdr' with value '1'. If the device isn't supporting this feature, the default value (96B) will be used. Signed-off-by: Michal Krawczyk <mk@semihalf.com> Reviewed-by: Igor Chauskin <igorch@amazon.com> Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
2020-04-08 08:29:10 +00:00
* **Updated Amazon ena driver.**
Updated ena PMD with new features and improvements, including:
* Added support for large LLQ (Low-latency queue) headers.
net/ena: add Tx drops statistic ENA device can report in the AENQ handler amount of Tx packets that were dropped and not sent. This statistic is showing global value for the device and because rte_eth_stats is missing field that could indicate this value (it isn't the Tx error), it is being presented as a extended statistic. As the current design of extended statistics prevents tx_drops from being an atomic variable and both tx_drops and rx_drops are only updated from the AENQ handler, both were set as non-atomic for the alignment. Signed-off-by: Michal Krawczyk <mk@semihalf.com> Reviewed-by: Igor Chauskin <igorch@amazon.com> Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
2020-04-08 08:29:12 +00:00
* Added Tx drops as new extended driver statistic.
net/ena: disable meta caching In the LLQ (Low-latency queue) mode, the device can indicate that meta data descriptor caching is disabled. In that case the driver should send valid meta descriptor on every Tx packet. Signed-off-by: Michal Krawczyk <mk@semihalf.com> Reviewed-by: Igor Chauskin <igorch@amazon.com> Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
2020-04-08 08:29:13 +00:00
* Added support for accelerated LLQ mode.
net/ena: reuse zero length Rx descriptor Some ENA devices can pass to the driver descriptor with length 0. To avoid extra allocation, the descriptor can be reused by simply putting it back to the device. Signed-off-by: Michal Krawczyk <mk@semihalf.com> Reviewed-by: Igor Chauskin <igorch@amazon.com> Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
2020-04-08 08:29:19 +00:00
* Handling of the 0 length descriptors on the Rx path.
net/ena: support large LLQ headers Default LLQ (Low-latency queue) maximum header size is 96 bytes and can be too small for some types of packets - like IPv6 packets with multiple extension. This can be fixed, by using large LLQ headers. If the device supports larger LLQ headers, the user can activate them by using device argument 'large_llq_hdr' with value '1'. If the device isn't supporting this feature, the default value (96B) will be used. Signed-off-by: Michal Krawczyk <mk@semihalf.com> Reviewed-by: Igor Chauskin <igorch@amazon.com> Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
2020-04-08 08:29:10 +00:00
net/i40e: enable MAC address as flow director input set Enable source MAC address and destination MAC address as FDIR's input set for ipv4-other, ipv4-udp and ipv4-tcp. When OVS-DPDK is working as a pure L2 switch, enable MAC address as FDIR input set with Mark+RSS action would help the performance speed up. And FVL FDIR supports to change input set with MAC address. Signed-off-by: Lunyuan Cui <lunyuanx.cui@intel.com> Acked-by: Beilei Xing <beilei.xing@intel.com>
2020-04-02 07:58:47 +00:00
* **Updated Intel i40e driver.**
Updated i40e PMD with new features and improvements, including:
* Enable MAC address as FDIR input set for ipv4-other, ipv4-udp and ipv4-tcp.
net/i40e: support hash configuration in RSS flow This patch supports: - Symmetric hash configuration - Hash input set configuration Signed-off-by: Chenxu Di <chenxux.di@intel.com> Acked-by: Beilei Xing <beilei.xing@intel.com>
2020-04-15 08:46:09 +00:00
* Added support for RSS using L3/L4 source/destination only.
* Added support for setting hash function in rte flow.
net/i40e: enable MAC address as flow director input set Enable source MAC address and destination MAC address as FDIR's input set for ipv4-other, ipv4-udp and ipv4-tcp. When OVS-DPDK is working as a pure L2 switch, enable MAC address as FDIR input set with Mark+RSS action would help the performance speed up. And FVL FDIR supports to change input set with MAC address. Signed-off-by: Lunyuan Cui <lunyuanx.cui@intel.com> Acked-by: Beilei Xing <beilei.xing@intel.com>
2020-04-02 07:58:47 +00:00
net/iavf: support generic flow API This patch added iavf_flow_create, iavf_flow_destroy, iavf_flow_flush and iavf_flow_validate support, these are used to handle all the generic filters. This patch supported basic L2, L3, L4 and GTPU patterns. Signed-off-by: Qiming Yang <qiming.yang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-04-03 05:42:41 +00:00
* **Updated the Intel iavf driver.**
Update the Intel iavf driver with new features and improvements, including:
* Added generic filter support.
net/iavf: support flow director basic rule This patch adds FDIR create/destroy/validate function in AVF. Common pattern and queue/qgroup/passthru/drop actions are supported. Signed-off-by: Simei Su <simei.su@intel.com> Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
2020-04-21 06:19:26 +00:00
* Added advanced iavf with FDIR capability.
net/iavf: add RSS configuration for VF The VF must be capable of configuring RSS. Add a virtchnl handler to parse a specific RSS configuration, and process the configuration for VFs, such as add or delete a RSS rule. Signed-off-by: Jeff Guo <jia.guo@intel.com> Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
2020-04-22 01:02:54 +00:00
* Added advanced RSS configuration for VFs.
net/iavf: support generic flow API This patch added iavf_flow_create, iavf_flow_destroy, iavf_flow_flush and iavf_flow_validate support, these are used to handle all the generic filters. This patch supported basic L2, L3, L4 and GTPU patterns. Signed-off-by: Qiming Yang <qiming.yang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-04-03 05:42:41 +00:00
net/ice: add DCF hardware initialization Introduce the DCF (Device Config Function) feature in the ice PMD, it works as a standalone PMD which doesn't handle the packet Rx/Tx related things. Its hardware entity is the VF. Add the basic DCF hardware initialization, this is specified by devarg 'cap=dcf'. Signed-off-by: Haiyue Wang <haiyue.wang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-03-27 02:56:36 +00:00
* **Updated the Intel ice driver.**
Updated the Intel ice driver with new features and improvements, including:
* Added support for DCF (Device Config Function) feature.
net/ice: enable switch flow on DCF DCF on CVL is a control plane VF which take the responsibility to configure all the PF/global resources, this patch add support DCF on to program forward rule to direct packets to VFs. Signed-off-by: Wei Zhao <wei.zhao1@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-04-03 04:45:57 +00:00
* Added switch filter support for intel DCF.
net/ice: add DCF hardware initialization Introduce the DCF (Device Config Function) feature in the ice PMD, it works as a standalone PMD which doesn't handle the packet Rx/Tx related things. Its hardware entity is the VF. Add the basic DCF hardware initialization, this is specified by devarg 'cap=dcf'. Signed-off-by: Haiyue Wang <haiyue.wang@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-03-27 02:56:36 +00:00
net/octeontx2: add TM capability Add Traffic Management capability callbacks to provide global, level and node capabilities. This patch also adds documentation on Traffic Management Support. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Krzysztof Kanas <kkanas@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-04-05 21:16:57 +00:00
* **Updated Marvell OCTEON TX2 ethdev driver.**
Updated Marvell OCTEON TX2 ethdev driver with traffic manager support with
below features.
* Hierarchial Scheduling with DWRR and SP.
* Single rate - Two color, Two rate - Three color shaping.
net/mlx5: support match on IPv4 TTL and IPv6 HLIM This patch adds to MLX5 PMD the support of matching on IPv4 TTL and IPv6 hoplimit. Support is valid when using DV flow engine (Verbs flow engine doesn't support matching on this field). Signed-off-by: Eli Britstein <elibr@mellanox.com> Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2020-03-03 12:37:31 +00:00
* **Updated Mellanox mlx5 driver.**
Updated Mellanox mlx5 driver with new features and improvements, including:
* Added support for matching on IPv4 Time To Live and IPv6 Hop Limit.
net/mlx5: create relaxed ordering memory regions In the current state, when preforming read/write transactions we must wait for a completion in order to run the next transaction, and all transactions are performed by order. Relaxed Ordering is a PCI optimization which by enabling it we allow the system to perform read/writes in a different order without having to wait for completion and improve the performance in that matter. This commit introduces the creation of relaxed ordering memory regions in mlx5. As relaxed ordering is an optimization, drivers that do not support it can simply ignore it and therefore it is enabled by default. Signed-off-by: Shiri Kuzin <shirik@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2020-03-24 11:39:39 +00:00
* Added support for creating Relaxed Ordering Memory Regions.
doc: add hairpin buffer size config in mlx5 guide This patch updates the MLX5 PMD and release notes documentations. Adding the guideline for hairpin data buffer size configuration. Signed-off-by: Bing Zhao <bingz@mellanox.com> Acked-by: Ori Kam <orika@mellanox.com>
2020-04-22 03:11:20 +00:00
* Added support for configuring Hairpin queue data buffer size.
net/mlx5: add device parameter for MPRQ stride size Define a device parameter to configure log 2 of a stride size for MPRQ - mprq_log_stride_size. User is able to specify a stride size in a range allowed by an underlying hardware. The default stride size is defined as 2048 bytes to encompass most commonly used packet sizes in the Internet (MTU 1518 and less) and will be used in case a maximum configured packet size cannot fit into the largest possible stride size. Otherwise a stride size is set to a large enough value to encompass a whole packet. Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2020-04-09 22:23:51 +00:00
* Added support for jumbo frame size (9K MTU) in Multi-Packet RQ mode.
doc: explicit flow config behaviour in mlx5 guide This patch updates the MLX5 PMD and release notes documentations. Adding the notes of the behavior change that rte flows organization is switched into non-cached mode for applications. Signed-off-by: Bing Zhao <bingz@mellanox.com> Acked-by: Ori Kam <orika@mellanox.com>
2020-04-22 15:27:15 +00:00
* Removed flow rules caching for memory saving and compliance with ethdev API.
doc: add mlx5 flow memory optimization to release notes Add flow memory optimization item. Signed-off-by: Suanming Mou <suanmingm@mellanox.com> Acked-by: Raslan Darawsheh <rasland@mellanox.com>
2020-04-20 06:53:44 +00:00
* Optimized the memory consumption of flow.
net/mlx5: support flow aging Currently, there is no flow aging check and age-out event callback mechanism for mlx5 driver, this patch implements it. It's included: - Splitting the current counter container to aged or no-aged container since reducing memory consumption. Aged container will allocate extra memory to save the aging parameter from user configuration. - Aging check and age-out event callback mechanism based on current counter. When a flow be checked aged-out, RTE_ETH_EVENT_FLOW_AGED event will be triggered to applications. - Implement the new API: rte_flow_get_aged_flows, applications can use this API to get aged flows. Signed-off-by: Dong Zhou <dongz@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2020-04-29 02:25:09 +00:00
* Added support for flow aging based on hardware counter.
net/mlx5: fix match on empty VLAN item in DV mode In existing implementation, using wild card VLAN item is not allowed. A VLAN item in flow pattern must include VLAN ID (vid) value. This obligation contradict the flow API specification [1]. This patch updates the VLAN item validation and translation, to allow wild card VLAN item, without VLAN ID value. User guide and release notes are updated accordingly. [1] commit 40513808b165 ("doc: refine ethernet and VLAN flow rule items") Fixes: 00f75a40576b ("net/mlx5: fix VLAN match for DV mode") Cc: stable@dpdk.org Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2020-05-05 12:57:54 +00:00
* Added support for flow pattern with wildcard VLAN item (without VID value).
net/mlx5: support match on IPv4 TTL and IPv6 HLIM This patch adds to MLX5 PMD the support of matching on IPv4 TTL and IPv6 hoplimit. Support is valid when using DV flow engine (Verbs flow engine doesn't support matching on this field). Signed-off-by: Eli Britstein <elibr@mellanox.com> Signed-off-by: Dekel Peled <dekelp@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
2020-03-03 12:37:31 +00:00
cryptodev: add ChaCha20-Poly1305 AEAD algorithm This patch adds Chacha20-Poly1305 AEAD algorithm to Cryptodev. Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com> Acked-by: Anoob Joseph <anoobj@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-05-07 10:57:02 +00:00
* **Added Chacha20-Poly1305 algorithm to Cryptodev API.**
Chacha20-Poly1305 AEAD algorithm can now be supported in Cryptodev.
crypto/aesni_mb: support DOCSIS AES-256 This patch adds support for DOCSIS AES-256 when using AESNI-MB Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-15 11:51:35 +00:00
* **Updated the AESNI MB crypto PMD.**
doc: support IPsec Multi-buffer lib v0.54 Updated AESNI MB and AESNI GCM PMD documentation guides with information about the latest Intel IPSec Multi-buffer library supported. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-17 22:00:37 +00:00
* Added support for intel-ipsec-mb version 0.54.
crypto/aesni_mb: support DOCSIS AES-256 This patch adds support for DOCSIS AES-256 when using AESNI-MB Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-15 11:51:35 +00:00
* Updated the AESNI MB PMD with AES-256 DOCSIS algorithm.
crypto/aesni_mb: support CPU crypto Add support for CPU crypto mode by introducing required handler. Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-17 15:03:48 +00:00
* Added support for synchronous Crypto burst API.
crypto/aesni_mb: support DOCSIS AES-256 This patch adds support for DOCSIS AES-256 when using AESNI-MB Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com> Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-15 11:51:35 +00:00
doc: support IPsec Multi-buffer lib v0.54 Updated AESNI MB and AESNI GCM PMD documentation guides with information about the latest Intel IPSec Multi-buffer library supported. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-17 22:00:37 +00:00
* **Updated the AESNI GCM crypto PMD.**
* Added support for intel-ipsec-mb version 0.54.
crypto/zuc: support IPsec Multi-buffer lib v0.54 The latest version of the Intel IPSec Multi-buffer library adds an API to authenticate multiple buffers in parallel. The PMD is modified to use this API, improving performance of the ZUC-EIA3 algorithm. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-05-11 09:14:20 +00:00
* **Updated the ZUC crypto PMD.**
* Added support for intel-ipsec-mb version 0.54.
* Updated the PMD to support Multi-buffer ZUC-EIA3,
improving performance significantly, when using
intel-ipsec-mb version 0.54
doc: support IPsec Multi-buffer lib v0.54 Updated SNOW3G and KASUMI PMD documentation guides with information about the latest Intel IPSec Multi-buffer library supported. Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-05-11 09:14:21 +00:00
* **Updated the SNOW3G crypto PMD.**
* Added support for intel-ipsec-mb version 0.54.
* **Updated the KASUMI crypto PMD.**
* Added support for intel-ipsec-mb version 0.54.
net/igc: add skeleton Implement device detection and loading. Add igc driver guide docs. Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-04-15 08:48:00 +00:00
* **Added a new driver for Intel Foxville I225 devices.**
Added the new ``igc`` net driver for Intel Foxville I225 devices. See the
:doc:`../nics/igc` NIC guide for more details on this new driver.
net/bnxt: enable meson build on TruFlow Include tf_ulp & tf_core directories and the files inside them. Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2020-04-15 08:19:11 +00:00
* **Updated Broadcom bnxt driver.**
Updated Broadcom bnxt driver with new features and improvements, including:
* Added support for host based flow table management
net/bnxt: add flow stats in extended stats This patch allows to display flow stats in extended stats. To do this, DMA-able memory is registered with the FW during device initialization. Then the driver uses an alarm thread to query the per flow stats using the HWRM_CFA_COUNTER_QSTATS HWRM command at regular intervals and stores it locally which will be displayed when the application queries the xstats. The DMA-able memory is unregistered during driver cleanup. This functionality can be enabled using the flow-xstat devarg and will be disabled by default. The intention behind this is to allow stats to be displayed for all the flows in one shot instead of querying one at a time. Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
2020-04-16 04:27:01 +00:00
* Added flow counters to extended stats
net/bnxt: add PCI function stats to extended stats HWRM API allows drivers to query stats per PCI function. These stats can provide some useful information in certain circumstances. Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
2020-04-02 05:26:29 +00:00
* Added PCI function stats to extended stats
net/bnxt: enable meson build on TruFlow Include tf_ulp & tf_core directories and the files inside them. Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com> Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2020-04-15 08:19:11 +00:00
crypto/qat: handle mixed hash-cipher on GEN2 This patch adds handling of mixed hash-cipher algorithms available on GEN2 QAT in particular firmware versions. Also the documentation is updated to show the mixed crypto algorithms are supported on QAT GEN2. Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-03-26 16:22:08 +00:00
* **Added handling of mixed crypto algorithms in QAT PMD for GEN2.**
Enabled handling of mixed algorithms in encrypted digest hash-cipher
(generation) and cipher-hash (verification) requests in QAT PMD
when running on GEN2 QAT hardware with particular firmware versions
(GEN3 support was added in DPDK 20.02).
crypto/qat: support plain SHA1..SHA512 hashes This patch adds support for plain SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashes to QAT PMD. Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-16 12:24:38 +00:00
* **Added plain SHA-1,224,256,384,512 support to QAT PMD.**
Added support for plain SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 hashes
to QAT PMD.
doc: add QAT AES-GCM J0 in release notes This patch adds missing line about addition of AES-GCM/GMAC J0 capability to 20.05 release notes. Fixes: 2165e2e9ea56 ("crypto/qat: support AES-GCM J0") Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com> Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
2020-05-07 09:19:49 +00:00
* **Added AES-GCM/GMAC J0 support to QAT PMD.**
Added support for AES-GCM/GMAC J0 to Intel QuickAssist Technology PMD. User can
use this feature by passing zero length IV in appropriate xform. For more
info please refer to rte_crypto_sym.h J0 comments.
compress/qat: support IM buffer too small operation This patch implements a special way of buffer handling when internal QAT IM buffer is too small for Huffman dynamic compression operation. Instead of falling back to fixed compression, the operation is now split into multiple smaller dynamic compression requests (possible to execute on QAT) and their results are then combined and copied into the output buffer. This is not possible if any checksum calculation was requested - in such case the code falls back to fixed compression as before. Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com> Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-17 15:44:03 +00:00
* **Added QAT intermediate buffer too small handling in QAT compression PMD.**
Added a special way of buffer handling when internal QAT intermediate buffer
is too small for Huffman dynamic compression operation. Instead of falling
back to fixed compression, the operation is now split into multiple smaller
dynamic compression requests (possible to execute on QAT) and their results
are then combined and copied into the output buffer. This is not possible if
any checksum calculation was requested - in such case the code falls back to
fixed compression as before.
baseband/turbo_sw: support large size code block This is to support cases when the input data for decoding a code block is larger than 64kB and would not fit as a contiguous block of data into one mbuf. In that case the length from the operation supersedes the mbuf default structure. Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Dave Burley <dave.burley@accelercomm.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-03-26 03:27:42 +00:00
* **Updated the turbo_sw bbdev PMD.**
Supported large size code blocks which does not fit in one mbuf segment.
baseband/fpga_5gnr_fec: add PMD for FPGA 5GNR FEC Add stubs for the FPGA 5GNR FEC PMD Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Dave Burley <dave.burley@accelercomm.com> Acked-by: Niall Power <niall.power@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-18 22:46:38 +00:00
* **Added Intel FPGA_5GNR_FEC bbdev PMD.**
Added a new ``fpga_5gnr_fec`` bbdev driver for the Intel\ |reg| FPGA PAC
(Programmable Acceleration Card) N3000. See the
:doc:`../bbdevs/fpga_5gnr_fec` BBDEV guide for more details on this new driver.
examples/ipsec-secgw: support 192/256 AES key sizes Adding support for the following, 1. AES-192-GCM 2. AES-256-GCM 3. AES-192-CBC Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-07 06:30:42 +00:00
* **Updated ipsec-secgw sample application with following features.**
doc: add event mode to ipsec-secgw Document addition of event mode support to ipsec-secgw application. Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-02-27 16:18:36 +00:00
examples/ipsec-secgw: support 192/256 AES key sizes Adding support for the following, 1. AES-192-GCM 2. AES-256-GCM 3. AES-192-CBC Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-07 06:30:42 +00:00
* Updated ipsec-secgw application to add event based packet processing.
The worker thread(s) would receive events and submit them back to the
event device after the processing. This way, multicore scaling and HW
assisted scheduling is achieved by making use of the event device
capabilities. The event mode currently supports only inline IPsec
protocol offload.
* Updated ipsec-secgw application to support key sizes for AES-192-CBC,
AES-192-GCM, AES-256-GCM algorithms.
doc: add event mode to ipsec-secgw Document addition of event mode support to ipsec-secgw application. Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-02-27 16:18:36 +00:00
examples/ipsec-secgw: support flow director Support load distribution in security gateway application using NIC load distribution feature (Flow Director). Flow Director is used to redirect the specified inbound ipsec flow to a specified queue. This is achieved by extending the SA rule syntax to support specification by adding new action_type of <flow-direction> to a specified <port_id> <queue_id>. Signed-off-by: Praveen Shetty <praveen.shetty@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-16 16:47:29 +00:00
* Added IPsec inbound load-distribution support for ipsec-secgw application
using NIC load distribution feature(Flow Director).
doc: update telemetry guides The existing documentation for Telemetry is updated, and further documentation is added. Signed-off-by: Ciara Power <ciara.power@intel.com> Reviewed-by: Keith Wiles <keith.wiles@intel.com>
2020-04-30 16:01:37 +00:00
* **Updated Telemetry Library.**
The updated Telemetry library has many improvements on the original version
to make it more accessible and scalable:
* It enables DPDK libraries and applications provide their own specific
telemetry information, rather than being limited to what could be reported
through the metrics library.
* It is no longer dependent on the external Jansson library, which allows
Telemetry be enabled by default.
* The socket handling has been simplified making it easier for clients to
connect and retrieve information.
doc: add graph library guide Adding programmer's guide for Graph library and the inbuilt nodes. This patch also updates the release note for the new libraries. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2020-04-11 14:14:27 +00:00
* **Added rte_graph library.**
Graph architecture abstracts the data processing functions as a ``node`` and
``links`` them together to create a complex ``graph`` to enable reusable/modular
data processing functions. The graph library provides API to enable graph
framework operations such as create, lookup, dump and destroy on graph and node
operations such as clone, edge update, and edge shrink, etc.
The API also allows to create the stats cluster to monitor per graph and per node stats.
* **Added rte_node library which consists of a set of packet processing nodes.**
The rte_node library that consists of nodes used by rte_graph library. Each
node performs a specific packet processing function based on application
configuration. The following nodes are added:
* Null node: Skeleton node that defines the general structure of a node.
* Ethernet device node: Consists of ethernet Rx/Tx nodes as well as ethernet
control APIs.
* IPv4 lookup node: Consists of ipv4 extract and lpm lookup node. Routes can
be configured by the application through ``rte_node_ip4_route_add`` function.
* IPv4 rewrite node: Consists of ipv4 and ethernet header rewrite functionality
that can be configured through ``rte_node_ip4_rewrite_add`` function.
* Packet drop node: Frees the packets received to their respective mempool.
doc: add l3fwd-graph application user guide Adding the user guide for l3fwd graph application. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2020-04-11 14:14:28 +00:00
* **Added new l3fwd-graph sample application.**
Added an example application ``l3fwd-graph``. It demonstrates the usage of graph
library and node library for packet processing. In addition to the library usage
demonstration, this application can use for performance comparison with existing
``l3fwd`` (The static code without any nodes) with the modular ``l3fwd-graph``
approach.
app/testpmd: add option for Rx multi-queue mode One new cmdline option `--rx-mq-mode` is added in order to have the possibility to check whether PMD handle the mq mode correctly or not. The reason is some NICs need to do different settings based on different RX mq mode, i.e RSS or not. With this support in testpmd, the above scenario can be tested easily. Signed-off-by: Xiaoyu Min <jackmin@mellanox.com> Acked-by: Bernard Iremonger <bernard.iremonger@intel.com>
2020-05-07 00:51:59 +00:00
* **Updated testpmd application.**
* Added a new cmdline option ``--rx-mq-mode`` which can be used to test PMD's
behaviour on handling Rx mq mode.
version: 20.05-rc0 Start a new release cycle with empty release notes. ABI must now be checked with v20.02 as a reference. Signed-off-by: David Marchand <david.marchand@redhat.com> Acked-by: Thomas Monjalon <thomas@monjalon.net>
2020-02-25 16:32:00 +00:00
Removed Items
-------------
.. This section should contain removed items in this release. Sample format:
* Add a short 1-2 sentence description of the removed item
in the past tense.
This section is a comment. Do not overwrite or remove it.
Also, make sure to start the actual text at the margin.
=========================================================
API Changes
-----------
.. This section should contain API changes. Sample format:
* sample: Add a short 1-2 sentence description of the API change
which was announced in the previous releases and made in this release.
Start with a scope label like "ethdev:".
Use fixed width quotes for ``function_names`` or ``struct_names``.
Use the past tense.
This section is a comment. Do not overwrite or remove it.
Also, make sure to start the actual text at the margin.
=========================================================
mempool: return 0 if area is too small on populate Change rte_mempool_populate_iova() and rte_mempool_populate_virt() to return 0 instead of -EINVAL when there is not enough room to store one object, as it can be helpful for applications to distinguish this specific case. As this is an ABI change, use symbol versioning to preserve old behavior for binary applications. Signed-off-by: Olivier Matz <olivier.matz@6wind.com> Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Andrew Rybchenko <arybchenko@solarflare.com> Acked-by: Lukasz Wojciechowski <l.wojciechow@partner.samsung.com>
2020-05-04 12:49:18 +00:00
* mempool: The API of ``rte_mempool_populate_iova()`` and
``rte_mempool_populate_virt()`` changed to return 0 instead of -EINVAL
when there is not enough room to store one object.
version: 20.05-rc0 Start a new release cycle with empty release notes. ABI must now be checked with v20.02 as a reference. Signed-off-by: David Marchand <david.marchand@redhat.com> Acked-by: Thomas Monjalon <thomas@monjalon.net>
2020-02-25 16:32:00 +00:00
ABI Changes
-----------
.. This section should contain ABI changes. Sample format:
* sample: Add a short 1-2 sentence description of the ABI change
which was announced in the previous releases and made in this release.
Start with a scope label like "ethdev:".
Use fixed width quotes for ``function_names`` or ``struct_names``.
Use the past tense.
This section is a comment. Do not overwrite or remove it.
Also, make sure to start the actual text at the margin.
=========================================================
* No ABI change that would break compatibility with DPDK 20.02 and 19.11.
Known Issues
------------
.. This section should contain new known issues in this release. Sample format:
* **Add title in present tense with full stop.**
Add a short 1-2 sentence description of the known issue
in the present tense. Add information on any known workarounds.
This section is a comment. Do not overwrite or remove it.
Also, make sure to start the actual text at the margin.
=========================================================
Tested Platforms
----------------
.. This section should contain a list of platforms that were tested
with this release.
The format is:
* <vendor> platform with <vendor> <type of devices> combinations
* List of CPU
* List of OS
* List of devices
* Other relevant details...
This section is a comment. Do not overwrite or remove it.
Also, make sure to start the actual text at the margin.
=========================================================
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