2014-02-10 15:27:26 +00:00
|
|
|
/*-
|
|
|
|
* BSD LICENSE
|
2014-06-03 23:42:50 +00:00
|
|
|
*
|
2015-05-15 15:56:59 +00:00
|
|
|
* Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
|
2014-02-10 15:27:26 +00:00
|
|
|
* All rights reserved.
|
2014-06-03 23:42:50 +00:00
|
|
|
*
|
2014-02-10 15:27:26 +00:00
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
2014-06-03 23:42:50 +00:00
|
|
|
*
|
2014-02-10 15:27:26 +00:00
|
|
|
* * Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in
|
|
|
|
* the documentation and/or other materials provided with the
|
|
|
|
* distribution.
|
|
|
|
* * Neither the name of Intel Corporation nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived
|
|
|
|
* from this software without specific prior written permission.
|
2014-06-03 23:42:50 +00:00
|
|
|
*
|
2014-02-10 15:27:26 +00:00
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <sys/queue.h>
|
|
|
|
#include <stdio.h>
|
|
|
|
#include <errno.h>
|
|
|
|
#include <stdint.h>
|
|
|
|
#include <string.h>
|
|
|
|
#include <unistd.h>
|
|
|
|
#include <stdarg.h>
|
|
|
|
#include <fcntl.h>
|
|
|
|
#include <inttypes.h>
|
|
|
|
#include <rte_byteorder.h>
|
|
|
|
#include <rte_common.h>
|
|
|
|
#include <rte_cycles.h>
|
|
|
|
|
|
|
|
#include <rte_interrupts.h>
|
|
|
|
#include <rte_log.h>
|
|
|
|
#include <rte_debug.h>
|
|
|
|
#include <rte_pci.h>
|
|
|
|
#include <rte_atomic.h>
|
|
|
|
#include <rte_branch_prediction.h>
|
|
|
|
#include <rte_memory.h>
|
|
|
|
#include <rte_memzone.h>
|
|
|
|
#include <rte_eal.h>
|
|
|
|
#include <rte_alarm.h>
|
|
|
|
#include <rte_ether.h>
|
|
|
|
#include <rte_ethdev.h>
|
|
|
|
#include <rte_atomic.h>
|
|
|
|
#include <rte_string_fns.h>
|
|
|
|
#include <rte_malloc.h>
|
2014-04-21 14:59:38 +00:00
|
|
|
#include <rte_dev.h>
|
2014-02-10 15:27:26 +00:00
|
|
|
|
2015-05-15 15:56:59 +00:00
|
|
|
#include "base/vmxnet3_defs.h"
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
#include "vmxnet3_ring.h"
|
|
|
|
#include "vmxnet3_logs.h"
|
|
|
|
#include "vmxnet3_ethdev.h"
|
|
|
|
|
|
|
|
#define PROCESS_SYS_EVENTS 0
|
|
|
|
|
2015-03-05 18:24:59 +00:00
|
|
|
static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
|
2015-10-27 17:12:26 +00:00
|
|
|
static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
|
2014-02-10 15:27:26 +00:00
|
|
|
static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
|
|
|
|
static int vmxnet3_dev_start(struct rte_eth_dev *dev);
|
|
|
|
static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
|
|
|
|
static void vmxnet3_dev_close(struct rte_eth_dev *dev);
|
|
|
|
static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
|
|
|
|
static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
|
|
|
|
static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
|
|
|
|
static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
|
|
|
|
static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
|
|
|
|
static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
|
|
|
|
int wait_to_complete);
|
|
|
|
static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
|
|
|
|
struct rte_eth_stats *stats);
|
|
|
|
static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
|
|
|
|
struct rte_eth_dev_info *dev_info);
|
2016-03-14 20:50:50 +00:00
|
|
|
static const uint32_t *
|
|
|
|
vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
|
2015-07-09 18:24:09 +00:00
|
|
|
static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
|
|
|
|
uint16_t vid, int on);
|
|
|
|
static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
|
2016-03-04 18:08:02 +00:00
|
|
|
static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
|
|
|
|
struct ether_addr *mac_addr);
|
2015-07-09 18:24:09 +00:00
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
#if PROCESS_SYS_EVENTS == 1
|
|
|
|
static void vmxnet3_process_events(struct vmxnet3_hw *);
|
|
|
|
#endif
|
|
|
|
/*
|
|
|
|
* The set of PCI devices this driver supports
|
|
|
|
*/
|
2015-04-16 23:23:39 +00:00
|
|
|
static const struct rte_pci_id pci_id_vmxnet3_map[] = {
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
#define RTE_PCI_DEV_ID_DECL_VMXNET3(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
|
|
|
|
#include "rte_pci_dev_ids.h"
|
|
|
|
|
|
|
|
{ .vendor_id = 0, /* sentinel */ },
|
|
|
|
};
|
|
|
|
|
2015-04-07 21:21:03 +00:00
|
|
|
static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
|
2014-02-10 15:27:26 +00:00
|
|
|
.dev_configure = vmxnet3_dev_configure,
|
|
|
|
.dev_start = vmxnet3_dev_start,
|
|
|
|
.dev_stop = vmxnet3_dev_stop,
|
|
|
|
.dev_close = vmxnet3_dev_close,
|
|
|
|
.promiscuous_enable = vmxnet3_dev_promiscuous_enable,
|
|
|
|
.promiscuous_disable = vmxnet3_dev_promiscuous_disable,
|
|
|
|
.allmulticast_enable = vmxnet3_dev_allmulticast_enable,
|
|
|
|
.allmulticast_disable = vmxnet3_dev_allmulticast_disable,
|
|
|
|
.link_update = vmxnet3_dev_link_update,
|
|
|
|
.stats_get = vmxnet3_dev_stats_get,
|
2016-03-04 18:08:02 +00:00
|
|
|
.mac_addr_set = vmxnet3_mac_addr_set,
|
2014-02-10 15:27:26 +00:00
|
|
|
.dev_infos_get = vmxnet3_dev_info_get,
|
2016-03-14 20:50:50 +00:00
|
|
|
.dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
|
2015-07-09 18:24:09 +00:00
|
|
|
.vlan_filter_set = vmxnet3_dev_vlan_filter_set,
|
|
|
|
.vlan_offload_set = vmxnet3_dev_vlan_offload_set,
|
2014-02-10 15:27:26 +00:00
|
|
|
.rx_queue_setup = vmxnet3_dev_rx_queue_setup,
|
|
|
|
.rx_queue_release = vmxnet3_dev_rx_queue_release,
|
|
|
|
.tx_queue_setup = vmxnet3_dev_tx_queue_setup,
|
|
|
|
.tx_queue_release = vmxnet3_dev_tx_queue_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct rte_memzone *
|
|
|
|
gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
|
|
|
|
const char *post_string, int socket_id, uint16_t align)
|
|
|
|
{
|
|
|
|
char z_name[RTE_MEMZONE_NAMESIZE];
|
|
|
|
const struct rte_memzone *mz;
|
|
|
|
|
2014-06-24 18:15:28 +00:00
|
|
|
snprintf(z_name, sizeof(z_name), "%s_%d_%s",
|
2014-02-10 15:27:26 +00:00
|
|
|
dev->driver->pci_drv.name, dev->data->port_id, post_string);
|
|
|
|
|
|
|
|
mz = rte_memzone_lookup(z_name);
|
|
|
|
if (mz)
|
|
|
|
return mz;
|
|
|
|
|
|
|
|
return rte_memzone_reserve_aligned(z_name, size,
|
|
|
|
socket_id, 0, align);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Atomically reads the link status information from global
|
|
|
|
* structure rte_eth_dev.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* - Pointer to the structure rte_eth_dev to read from.
|
|
|
|
* - Pointer to the buffer to be saved with the link status.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* - On success, zero.
|
|
|
|
* - On failure, negative value.
|
|
|
|
*/
|
2015-07-09 18:24:13 +00:00
|
|
|
|
|
|
|
static int
|
|
|
|
vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
|
|
|
|
struct rte_eth_link *link)
|
|
|
|
{
|
|
|
|
struct rte_eth_link *dst = link;
|
|
|
|
struct rte_eth_link *src = &(dev->data->dev_link);
|
|
|
|
|
|
|
|
if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
|
|
|
|
*(uint64_t *)src) == 0)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Atomically writes the link status information into global
|
|
|
|
* structure rte_eth_dev.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* - Pointer to the structure rte_eth_dev to write to.
|
|
|
|
* - Pointer to the buffer to be saved with the link status.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* - On success, zero.
|
|
|
|
* - On failure, negative value.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
|
|
|
|
struct rte_eth_link *link)
|
2014-02-10 15:27:26 +00:00
|
|
|
{
|
|
|
|
struct rte_eth_link *dst = &(dev->data->dev_link);
|
|
|
|
struct rte_eth_link *src = link;
|
|
|
|
|
|
|
|
if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
|
|
|
|
*(uint64_t *)src) == 0)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is based on vmxnet3_disable_intr()
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
vmxnet3_disable_intr(struct vmxnet3_hw *hw)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
|
|
|
|
for (i = 0; i < VMXNET3_MAX_INTRS; i++)
|
|
|
|
VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It returns 0 on success.
|
|
|
|
*/
|
|
|
|
static int
|
2015-03-05 18:24:59 +00:00
|
|
|
eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
|
2014-02-10 15:27:26 +00:00
|
|
|
{
|
|
|
|
struct rte_pci_device *pci_dev;
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = eth_dev->data->dev_private;
|
2014-02-10 15:27:26 +00:00
|
|
|
uint32_t mac_hi, mac_lo, ver;
|
|
|
|
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
|
|
|
|
eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
|
|
|
|
eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
|
|
|
|
pci_dev = eth_dev->pci_dev;
|
|
|
|
|
2014-06-03 23:42:50 +00:00
|
|
|
/*
|
2015-06-10 16:09:37 +00:00
|
|
|
* for secondary processes, we don't initialize any further as primary
|
2014-06-03 23:42:50 +00:00
|
|
|
* has already done this work.
|
|
|
|
*/
|
2014-02-10 15:27:26 +00:00
|
|
|
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
|
|
|
|
return 0;
|
|
|
|
|
2015-11-03 13:01:56 +00:00
|
|
|
rte_eth_copy_pci_info(eth_dev, pci_dev);
|
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
/* Vendor and Device ID need to be set before init of shared code */
|
|
|
|
hw->device_id = pci_dev->id.device_id;
|
|
|
|
hw->vendor_id = pci_dev->id.vendor_id;
|
|
|
|
hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
|
|
|
|
hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
|
|
|
|
|
|
|
|
hw->num_rx_queues = 1;
|
|
|
|
hw->num_tx_queues = 1;
|
|
|
|
hw->bufs_per_pkt = 1;
|
|
|
|
|
|
|
|
/* Check h/w version compatibility with driver. */
|
2014-06-13 01:37:04 +00:00
|
|
|
ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
|
2015-06-10 16:09:37 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
|
2014-06-13 01:37:04 +00:00
|
|
|
if (ver & 0x1)
|
2014-06-03 23:42:50 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1);
|
2014-06-13 01:37:04 +00:00
|
|
|
else {
|
2015-06-10 16:09:37 +00:00
|
|
|
PMD_INIT_LOG(ERR, "Incompatible h/w version, should be 0x1");
|
2014-06-03 23:42:50 +00:00
|
|
|
return -EIO;
|
2014-06-13 01:37:04 +00:00
|
|
|
}
|
2014-02-10 15:27:26 +00:00
|
|
|
|
2014-06-13 01:37:04 +00:00
|
|
|
/* Check UPT version compatibility with driver. */
|
|
|
|
ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
|
2015-06-10 16:09:37 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
|
2014-06-13 01:37:04 +00:00
|
|
|
if (ver & 0x1)
|
2014-06-03 23:42:50 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
|
2014-06-13 01:37:04 +00:00
|
|
|
else {
|
2015-06-10 16:09:37 +00:00
|
|
|
PMD_INIT_LOG(ERR, "Incompatible UPT version.");
|
2014-06-03 23:42:50 +00:00
|
|
|
return -EIO;
|
2014-06-13 01:37:04 +00:00
|
|
|
}
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
/* Getting MAC Address */
|
|
|
|
mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
|
|
|
|
mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
|
|
|
|
memcpy(hw->perm_addr , &mac_lo, 4);
|
|
|
|
memcpy(hw->perm_addr+4, &mac_hi, 2);
|
|
|
|
|
|
|
|
/* Allocate memory for storing MAC addresses */
|
|
|
|
eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
|
2014-06-13 01:37:04 +00:00
|
|
|
VMXNET3_MAX_MAC_ADDRS, 0);
|
2014-02-10 15:27:26 +00:00
|
|
|
if (eth_dev->data->mac_addrs == NULL) {
|
|
|
|
PMD_INIT_LOG(ERR,
|
2014-06-13 01:37:04 +00:00
|
|
|
"Failed to allocate %d bytes needed to store MAC addresses",
|
|
|
|
ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
|
2014-02-10 15:27:26 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
/* Copy the permanent MAC address */
|
|
|
|
ether_addr_copy((struct ether_addr *) hw->perm_addr,
|
|
|
|
ð_dev->data->mac_addrs[0]);
|
|
|
|
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
|
2014-06-13 01:37:04 +00:00
|
|
|
hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
|
|
|
|
hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
/* Put device in Quiesce Mode */
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
|
|
|
|
|
2016-03-04 18:08:01 +00:00
|
|
|
/* allow untagged pkts */
|
|
|
|
VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
|
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-10-27 17:12:26 +00:00
|
|
|
static int
|
|
|
|
eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
|
|
|
|
{
|
|
|
|
struct vmxnet3_hw *hw = eth_dev->data->dev_private;
|
|
|
|
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (hw->adapter_stopped == 0)
|
|
|
|
vmxnet3_dev_close(eth_dev);
|
|
|
|
|
|
|
|
eth_dev->dev_ops = NULL;
|
|
|
|
eth_dev->rx_pkt_burst = NULL;
|
|
|
|
eth_dev->tx_pkt_burst = NULL;
|
|
|
|
|
|
|
|
rte_free(eth_dev->data->mac_addrs);
|
|
|
|
eth_dev->data->mac_addrs = NULL;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
static struct eth_driver rte_vmxnet3_pmd = {
|
2015-05-29 15:47:51 +00:00
|
|
|
.pci_drv = {
|
2014-02-10 15:27:26 +00:00
|
|
|
.name = "rte_vmxnet3_pmd",
|
|
|
|
.id_table = pci_id_vmxnet3_map,
|
2015-10-27 17:12:26 +00:00
|
|
|
.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
|
2014-02-10 15:27:26 +00:00
|
|
|
},
|
|
|
|
.eth_dev_init = eth_vmxnet3_dev_init,
|
2015-10-27 17:12:26 +00:00
|
|
|
.eth_dev_uninit = eth_vmxnet3_dev_uninit,
|
2014-06-13 01:39:58 +00:00
|
|
|
.dev_private_size = sizeof(struct vmxnet3_hw),
|
2014-02-10 15:27:26 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Driver initialization routine.
|
|
|
|
* Invoked once at EAL init time.
|
|
|
|
* Register itself as the [Poll Mode] Driver of Virtual PCI VMXNET3 devices.
|
|
|
|
*/
|
2014-04-21 14:59:38 +00:00
|
|
|
static int
|
|
|
|
rte_vmxnet3_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
|
2014-02-10 15:27:26 +00:00
|
|
|
{
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
rte_eth_driver_register(&rte_vmxnet3_pmd);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
vmxnet3_dev_configure(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
const struct rte_memzone *mz;
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2014-02-10 15:27:26 +00:00
|
|
|
size_t size;
|
|
|
|
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
if (dev->data->nb_rx_queues > UINT8_MAX ||
|
2014-06-13 01:37:04 +00:00
|
|
|
dev->data->nb_tx_queues > UINT8_MAX)
|
|
|
|
return -EINVAL;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
|
2014-06-13 01:37:04 +00:00
|
|
|
dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
if (size > UINT16_MAX)
|
2014-06-13 01:37:04 +00:00
|
|
|
return -EINVAL;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
|
|
|
|
hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
|
|
|
|
|
2014-06-03 23:42:50 +00:00
|
|
|
/*
|
|
|
|
* Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
|
2014-02-10 15:27:26 +00:00
|
|
|
* on current socket
|
|
|
|
*/
|
2014-06-13 01:37:04 +00:00
|
|
|
mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
|
|
|
|
"shared", rte_socket_id(), 8);
|
2014-06-03 23:42:50 +00:00
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
if (mz == NULL) {
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
|
2014-06-13 01:37:04 +00:00
|
|
|
return -ENOMEM;
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
memset(mz->addr, 0, mz->len);
|
|
|
|
|
|
|
|
hw->shared = mz->addr;
|
|
|
|
hw->sharedPA = mz->phys_addr;
|
|
|
|
|
2014-06-03 23:42:50 +00:00
|
|
|
/*
|
2014-06-13 01:37:04 +00:00
|
|
|
* Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
|
|
|
|
* on current socket
|
|
|
|
*/
|
2014-02-10 15:27:26 +00:00
|
|
|
mz = gpa_zone_reserve(dev, size, "queuedesc",
|
2014-06-13 01:37:04 +00:00
|
|
|
rte_socket_id(), VMXNET3_QUEUE_DESC_ALIGN);
|
2014-02-10 15:27:26 +00:00
|
|
|
if (mz == NULL) {
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
|
2014-06-13 01:37:04 +00:00
|
|
|
return -ENOMEM;
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
memset(mz->addr, 0, mz->len);
|
|
|
|
|
|
|
|
hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
|
|
|
|
hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
|
|
|
|
|
|
|
|
hw->queueDescPA = mz->phys_addr;
|
|
|
|
hw->queue_desc_len = (uint16_t)size;
|
|
|
|
|
2014-06-13 01:37:04 +00:00
|
|
|
if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
/* Allocate memory structure for UPT1_RSSConf and configure */
|
2014-06-13 01:37:04 +00:00
|
|
|
mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf), "rss_conf",
|
2014-11-19 12:26:06 +00:00
|
|
|
rte_socket_id(), RTE_CACHE_LINE_SIZE);
|
2014-02-10 15:27:26 +00:00
|
|
|
if (mz == NULL) {
|
2014-06-13 01:37:04 +00:00
|
|
|
PMD_INIT_LOG(ERR,
|
2014-06-13 01:37:13 +00:00
|
|
|
"ERROR: Creating rss_conf structure zone");
|
2014-06-13 01:37:04 +00:00
|
|
|
return -ENOMEM;
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
memset(mz->addr, 0, mz->len);
|
|
|
|
|
|
|
|
hw->rss_conf = mz->addr;
|
|
|
|
hw->rss_confPA = mz->phys_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-04 18:08:02 +00:00
|
|
|
static void
|
|
|
|
vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
|
|
|
|
{
|
|
|
|
uint32_t val;
|
|
|
|
|
|
|
|
PMD_INIT_LOG(DEBUG,
|
|
|
|
"Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
|
|
|
|
addr[0], addr[1], addr[2],
|
|
|
|
addr[3], addr[4], addr[5]);
|
|
|
|
|
|
|
|
val = *(const uint32_t *)addr;
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
|
|
|
|
|
|
|
|
val = (addr[5] << 8) | addr[4];
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
|
|
|
|
}
|
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
static int
|
|
|
|
vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct rte_eth_conf port_conf = dev->data->dev_conf;
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2016-03-04 18:08:00 +00:00
|
|
|
uint32_t mtu = dev->data->mtu;
|
2014-02-10 15:27:26 +00:00
|
|
|
Vmxnet3_DriverShared *shared = hw->shared;
|
|
|
|
Vmxnet3_DSDevRead *devRead = &shared->devRead;
|
2016-03-04 18:08:02 +00:00
|
|
|
uint32_t i;
|
2016-03-04 18:08:01 +00:00
|
|
|
int ret;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
shared->magic = VMXNET3_REV1_MAGIC;
|
|
|
|
devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
|
|
|
|
|
|
|
|
/* Setting up Guest OS information */
|
|
|
|
devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
|
2014-06-13 01:37:04 +00:00
|
|
|
VMXNET3_GOS_BITS_32 :
|
|
|
|
VMXNET3_GOS_BITS_64;
|
2014-02-10 15:27:26 +00:00
|
|
|
devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
|
|
|
|
devRead->misc.driverInfo.vmxnet3RevSpt = 1;
|
|
|
|
devRead->misc.driverInfo.uptVerSpt = 1;
|
|
|
|
|
2016-03-04 18:08:00 +00:00
|
|
|
devRead->misc.mtu = rte_le_to_cpu_32(mtu);
|
2014-02-10 15:27:26 +00:00
|
|
|
devRead->misc.queueDescPA = hw->queueDescPA;
|
|
|
|
devRead->misc.queueDescLen = hw->queue_desc_len;
|
|
|
|
devRead->misc.numTxQueues = hw->num_tx_queues;
|
|
|
|
devRead->misc.numRxQueues = hw->num_rx_queues;
|
|
|
|
|
|
|
|
/*
|
2014-06-13 01:37:04 +00:00
|
|
|
* Set number of interrupts to 1
|
|
|
|
* PMD disables all the interrupts but this is MUST to activate device
|
|
|
|
* It needs at least one interrupt for link events to handle
|
|
|
|
* So we'll disable it later after device activation if needed
|
|
|
|
*/
|
2014-02-10 15:27:26 +00:00
|
|
|
devRead->intrConf.numIntrs = 1;
|
|
|
|
devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
|
|
|
|
|
|
|
|
for (i = 0; i < hw->num_tx_queues; i++) {
|
|
|
|
Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
|
2014-11-05 01:49:43 +00:00
|
|
|
vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
tqd->ctrl.txNumDeferred = 0;
|
|
|
|
tqd->ctrl.txThreshold = 1;
|
|
|
|
tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
|
|
|
|
tqd->conf.compRingBasePA = txq->comp_ring.basePA;
|
2014-11-05 01:49:43 +00:00
|
|
|
tqd->conf.dataRingBasePA = txq->data_ring.basePA;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
tqd->conf.txRingSize = txq->cmd_ring.size;
|
|
|
|
tqd->conf.compRingSize = txq->comp_ring.size;
|
2014-11-05 01:49:43 +00:00
|
|
|
tqd->conf.dataRingSize = txq->data_ring.size;
|
2014-02-10 15:27:26 +00:00
|
|
|
tqd->conf.intrIdx = txq->comp_ring.intr_idx;
|
|
|
|
tqd->status.stopped = TRUE;
|
|
|
|
tqd->status.error = 0;
|
|
|
|
memset(&tqd->stats, 0, sizeof(tqd->stats));
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < hw->num_rx_queues; i++) {
|
|
|
|
Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
|
2014-11-05 01:49:43 +00:00
|
|
|
vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
|
|
|
|
rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
|
|
|
|
rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
|
|
|
|
|
|
|
|
rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
|
|
|
|
rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
|
|
|
|
rqd->conf.compRingSize = rxq->comp_ring.size;
|
|
|
|
rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
|
|
|
|
rqd->status.stopped = TRUE;
|
|
|
|
rqd->status.error = 0;
|
|
|
|
memset(&rqd->stats, 0, sizeof(rqd->stats));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* RxMode set to 0 of VMXNET3_RXM_xxx */
|
|
|
|
devRead->rxFilterConf.rxMode = 0;
|
|
|
|
|
|
|
|
/* Setting up feature flags */
|
2014-06-13 01:37:04 +00:00
|
|
|
if (dev->data->dev_conf.rxmode.hw_ip_checksum)
|
2014-02-10 15:27:26 +00:00
|
|
|
devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
|
|
|
|
|
2014-06-13 01:37:04 +00:00
|
|
|
if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
|
2014-02-10 15:27:26 +00:00
|
|
|
ret = vmxnet3_rss_configure(dev);
|
2014-06-13 01:37:04 +00:00
|
|
|
if (ret != VMXNET3_SUCCESS)
|
2014-02-10 15:27:26 +00:00
|
|
|
return ret;
|
2014-06-13 01:37:04 +00:00
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
devRead->misc.uptFeatures |= VMXNET3_F_RSS;
|
|
|
|
devRead->rssConfDesc.confVer = 1;
|
|
|
|
devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
|
|
|
|
devRead->rssConfDesc.confPA = hw->rss_confPA;
|
|
|
|
}
|
|
|
|
|
2016-03-04 18:08:01 +00:00
|
|
|
vmxnet3_dev_vlan_offload_set(dev,
|
|
|
|
ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
2016-03-04 18:08:02 +00:00
|
|
|
vmxnet3_write_mac(hw, hw->perm_addr);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
return VMXNET3_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure device link speed and setup link.
|
|
|
|
* Must be called after eth_vmxnet3_dev_init. Other wise it might fail
|
|
|
|
* It returns 0 on success.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
vmxnet3_dev_start(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
int status, ret;
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
ret = vmxnet3_setup_driver_shared(dev);
|
2014-06-13 01:37:04 +00:00
|
|
|
if (ret != VMXNET3_SUCCESS)
|
2014-02-10 15:27:26 +00:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Exchange shared data with device */
|
2014-06-13 01:37:04 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
|
|
|
|
VMXNET3_GET_ADDR_LO(hw->sharedPA));
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
|
|
|
|
VMXNET3_GET_ADDR_HI(hw->sharedPA));
|
2014-02-10 15:27:26 +00:00
|
|
|
|
2014-06-13 01:37:04 +00:00
|
|
|
/* Activate device by register write */
|
2014-02-10 15:27:26 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
|
|
|
|
status = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
|
|
|
|
|
|
|
|
if (status != 0) {
|
2016-02-10 16:12:39 +00:00
|
|
|
PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
|
2014-02-10 15:27:26 +00:00
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable interrupts */
|
|
|
|
vmxnet3_disable_intr(hw);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Load RX queues with blank mbufs and update next2fill index for device
|
|
|
|
* Update RxMode of the device
|
|
|
|
*/
|
|
|
|
ret = vmxnet3_dev_rxtx_init(dev);
|
2014-06-13 01:37:04 +00:00
|
|
|
if (ret != VMXNET3_SUCCESS) {
|
2016-02-10 16:12:39 +00:00
|
|
|
PMD_INIT_LOG(ERR, "Device receive init: UNSUCCESSFUL");
|
2014-02-10 15:27:26 +00:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Setting proper Rx Mode and issue Rx Mode Update command */
|
2014-07-25 17:50:37 +00:00
|
|
|
vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Don't need to handle events for now
|
|
|
|
*/
|
|
|
|
#if PROCESS_SYS_EVENTS == 1
|
|
|
|
events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events);
|
2014-02-10 15:27:26 +00:00
|
|
|
vmxnet3_process_events(hw);
|
|
|
|
#endif
|
|
|
|
return status;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Stop device: disable rx and tx functions to allow for reconfiguring.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
vmxnet3_dev_stop(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct rte_eth_link link;
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
2015-10-27 17:12:26 +00:00
|
|
|
if (hw->adapter_stopped == 1) {
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "Device already closed.");
|
2014-02-10 15:27:26 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* disable interrupts */
|
|
|
|
vmxnet3_disable_intr(hw);
|
|
|
|
|
|
|
|
/* quiesce the device first */
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
|
|
|
|
|
|
|
|
/* reset the device */
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "Device reset.");
|
2015-10-27 17:12:26 +00:00
|
|
|
hw->adapter_stopped = 0;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
vmxnet3_dev_clear_queues(dev);
|
|
|
|
|
|
|
|
/* Clear recorded link status */
|
|
|
|
memset(&link, 0, sizeof(link));
|
2015-07-09 18:24:13 +00:00
|
|
|
vmxnet3_dev_atomic_write_link_status(dev, &link);
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset and stop device.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
vmxnet3_dev_close(struct rte_eth_dev *dev)
|
|
|
|
{
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
vmxnet3_dev_stop(dev);
|
2015-10-27 17:12:26 +00:00
|
|
|
hw->adapter_stopped = 1;
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2014-06-13 01:37:04 +00:00
|
|
|
vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
|
2014-02-10 15:27:26 +00:00
|
|
|
{
|
|
|
|
unsigned int i;
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
|
|
|
|
|
2014-06-13 01:38:47 +00:00
|
|
|
RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
|
2014-02-10 15:27:26 +00:00
|
|
|
for (i = 0; i < hw->num_tx_queues; i++) {
|
2014-06-13 01:38:47 +00:00
|
|
|
struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats;
|
|
|
|
|
|
|
|
stats->q_opackets[i] = txStats->ucastPktsTxOK +
|
|
|
|
txStats->mcastPktsTxOK +
|
|
|
|
txStats->bcastPktsTxOK;
|
|
|
|
stats->q_obytes[i] = txStats->ucastBytesTxOK +
|
|
|
|
txStats->mcastBytesTxOK +
|
|
|
|
txStats->bcastBytesTxOK;
|
|
|
|
|
|
|
|
stats->opackets += stats->q_opackets[i];
|
|
|
|
stats->obytes += stats->q_obytes[i];
|
|
|
|
stats->oerrors += txStats->pktsTxError +
|
|
|
|
txStats->pktsTxDiscard;
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
2014-06-13 01:38:47 +00:00
|
|
|
RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
|
2014-02-10 15:27:26 +00:00
|
|
|
for (i = 0; i < hw->num_rx_queues; i++) {
|
2014-06-13 01:38:47 +00:00
|
|
|
struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats;
|
|
|
|
|
|
|
|
stats->q_ipackets[i] = rxStats->ucastPktsRxOK +
|
|
|
|
rxStats->mcastPktsRxOK +
|
|
|
|
rxStats->bcastPktsRxOK;
|
2014-02-10 15:27:26 +00:00
|
|
|
|
2014-06-13 01:38:47 +00:00
|
|
|
stats->q_ibytes[i] = rxStats->ucastBytesRxOK +
|
|
|
|
rxStats->mcastBytesRxOK +
|
|
|
|
rxStats->bcastBytesRxOK;
|
|
|
|
|
|
|
|
stats->ipackets += stats->q_ipackets[i];
|
|
|
|
stats->ibytes += stats->q_ibytes[i];
|
|
|
|
|
|
|
|
stats->q_errors[i] = rxStats->pktsRxError;
|
|
|
|
stats->ierrors += rxStats->pktsRxError;
|
|
|
|
stats->imcasts += rxStats->mcastPktsRxOK;
|
|
|
|
stats->rx_nombuf += rxStats->pktsRxOutOfBuf;
|
|
|
|
}
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-01-13 02:08:37 +00:00
|
|
|
vmxnet3_dev_info_get(__attribute__((unused))struct rte_eth_dev *dev,
|
|
|
|
struct rte_eth_dev_info *dev_info)
|
2014-02-10 15:27:26 +00:00
|
|
|
{
|
|
|
|
dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
|
|
|
|
dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
|
|
|
|
dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
|
|
|
|
dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
|
|
|
|
dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
|
2014-12-11 21:18:40 +00:00
|
|
|
|
2016-03-28 22:35:55 +00:00
|
|
|
dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP;
|
2015-02-04 07:16:32 +00:00
|
|
|
dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
|
2015-10-27 12:51:49 +00:00
|
|
|
|
|
|
|
dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
|
|
|
|
.nb_max = VMXNET3_RX_RING_MAX_SIZE,
|
|
|
|
.nb_min = VMXNET3_DEF_RX_RING_SIZE,
|
|
|
|
.nb_align = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
|
|
|
|
.nb_max = VMXNET3_TX_RING_MAX_SIZE,
|
|
|
|
.nb_min = VMXNET3_DEF_TX_RING_SIZE,
|
|
|
|
.nb_align = 1,
|
|
|
|
};
|
2016-01-13 02:08:37 +00:00
|
|
|
|
|
|
|
dev_info->rx_offload_capa =
|
|
|
|
DEV_RX_OFFLOAD_VLAN_STRIP |
|
|
|
|
DEV_RX_OFFLOAD_UDP_CKSUM |
|
|
|
|
DEV_RX_OFFLOAD_TCP_CKSUM;
|
|
|
|
|
|
|
|
dev_info->tx_offload_capa =
|
|
|
|
DEV_TX_OFFLOAD_VLAN_INSERT |
|
|
|
|
DEV_TX_OFFLOAD_TCP_CKSUM |
|
|
|
|
DEV_TX_OFFLOAD_UDP_CKSUM |
|
|
|
|
DEV_TX_OFFLOAD_TCP_TSO;
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
2016-03-14 20:50:50 +00:00
|
|
|
static const uint32_t *
|
|
|
|
vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
static const uint32_t ptypes[] = {
|
|
|
|
RTE_PTYPE_L3_IPV4_EXT,
|
|
|
|
RTE_PTYPE_L3_IPV4,
|
|
|
|
RTE_PTYPE_UNKNOWN
|
|
|
|
};
|
|
|
|
|
|
|
|
if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
|
|
|
|
return ptypes;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2016-03-04 18:08:02 +00:00
|
|
|
static void
|
|
|
|
vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
|
|
|
|
{
|
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
|
|
|
|
|
|
|
vmxnet3_write_mac(hw, mac_addr->addr_bytes);
|
|
|
|
}
|
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
/* return 0 means link status changed, -1 means not changed */
|
|
|
|
static int
|
|
|
|
vmxnet3_dev_link_update(struct rte_eth_dev *dev, __attribute__((unused)) int wait_to_complete)
|
|
|
|
{
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2015-07-09 18:24:13 +00:00
|
|
|
struct rte_eth_link old, link;
|
2014-02-10 15:27:26 +00:00
|
|
|
uint32_t ret;
|
|
|
|
|
2015-07-09 18:24:13 +00:00
|
|
|
if (dev->data->dev_started == 0)
|
|
|
|
return -1; /* Link status doesn't change for stopped dev */
|
|
|
|
|
|
|
|
memset(&link, 0, sizeof(link));
|
|
|
|
vmxnet3_dev_atomic_read_link_status(dev, &old);
|
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
|
|
|
|
ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
|
|
|
|
|
|
|
|
if (ret & 0x1) {
|
2016-03-31 22:12:24 +00:00
|
|
|
link.link_status = ETH_LINK_UP;
|
2014-02-10 15:27:26 +00:00
|
|
|
link.link_duplex = ETH_LINK_FULL_DUPLEX;
|
|
|
|
link.link_speed = ETH_LINK_SPEED_10000;
|
|
|
|
}
|
|
|
|
|
2015-07-09 18:24:13 +00:00
|
|
|
vmxnet3_dev_atomic_write_link_status(dev, &link);
|
|
|
|
|
|
|
|
return (old.link_status == link.link_status) ? -1 : 0;
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
|
|
|
|
static void
|
|
|
|
vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set) {
|
|
|
|
|
|
|
|
struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
|
2014-06-13 01:37:04 +00:00
|
|
|
|
|
|
|
if (set)
|
2014-02-10 15:27:26 +00:00
|
|
|
rxConf->rxMode = rxConf->rxMode | feature;
|
|
|
|
else
|
|
|
|
rxConf->rxMode = rxConf->rxMode & (~feature);
|
|
|
|
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
|
|
|
|
static void
|
|
|
|
vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
|
|
|
|
{
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2015-07-09 18:24:09 +00:00
|
|
|
uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
|
2014-06-13 01:37:04 +00:00
|
|
|
|
2015-07-09 18:24:09 +00:00
|
|
|
memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
|
2014-02-10 15:27:26 +00:00
|
|
|
vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
|
2015-07-09 18:24:09 +00:00
|
|
|
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
|
|
|
|
VMXNET3_CMD_UPDATE_VLAN_FILTERS);
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
|
|
|
|
static void
|
|
|
|
vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
|
|
|
|
{
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2015-07-09 18:24:09 +00:00
|
|
|
uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
|
2014-06-13 01:37:04 +00:00
|
|
|
|
2015-07-09 18:24:09 +00:00
|
|
|
memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
|
2014-02-10 15:27:26 +00:00
|
|
|
vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
|
2015-07-09 18:24:09 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
|
|
|
|
VMXNET3_CMD_UPDATE_VLAN_FILTERS);
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
|
|
|
|
static void
|
|
|
|
vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
|
|
|
|
{
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2014-06-13 01:37:04 +00:00
|
|
|
|
2014-06-13 01:36:56 +00:00
|
|
|
vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
|
|
|
|
static void
|
|
|
|
vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
|
|
|
|
{
|
2014-06-13 01:39:58 +00:00
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
2014-06-13 01:37:04 +00:00
|
|
|
|
2014-06-13 01:36:56 +00:00
|
|
|
vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
2015-07-09 18:24:09 +00:00
|
|
|
/* Enable/disable filter on vlan */
|
|
|
|
static int
|
|
|
|
vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
|
|
|
|
{
|
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
|
|
|
struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
|
|
|
|
uint32_t *vf_table = rxConf->vfTable;
|
|
|
|
|
|
|
|
/* save state for restore */
|
|
|
|
if (on)
|
|
|
|
VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
|
|
|
|
else
|
|
|
|
VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
|
|
|
|
|
2016-01-13 02:08:32 +00:00
|
|
|
/* don't change active filter if in promiscuous mode */
|
2015-07-09 18:24:09 +00:00
|
|
|
if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* set in hardware */
|
|
|
|
if (on)
|
|
|
|
VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
|
|
|
|
else
|
|
|
|
VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
|
|
|
|
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
|
|
|
|
VMXNET3_CMD_UPDATE_VLAN_FILTERS);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2016-03-04 18:08:01 +00:00
|
|
|
vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
|
2015-07-09 18:24:09 +00:00
|
|
|
{
|
|
|
|
struct vmxnet3_hw *hw = dev->data->dev_private;
|
|
|
|
Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
|
|
|
|
uint32_t *vf_table = devRead->rxFilterConf.vfTable;
|
|
|
|
|
2016-03-04 18:08:01 +00:00
|
|
|
if (mask & ETH_VLAN_STRIP_MASK) {
|
|
|
|
if (dev->data->dev_conf.rxmode.hw_vlan_strip)
|
|
|
|
devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
|
|
|
|
else
|
|
|
|
devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
|
2015-07-09 18:24:09 +00:00
|
|
|
|
2016-03-04 18:08:01 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
|
|
|
|
VMXNET3_CMD_UPDATE_FEATURE);
|
2015-07-09 18:24:09 +00:00
|
|
|
}
|
|
|
|
|
2016-03-04 18:08:01 +00:00
|
|
|
if (mask & ETH_VLAN_FILTER_MASK) {
|
|
|
|
if (dev->data->dev_conf.rxmode.hw_vlan_filter)
|
|
|
|
memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
|
|
|
|
else
|
|
|
|
memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
|
2015-07-09 18:24:09 +00:00
|
|
|
|
2016-03-04 18:08:01 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
|
|
|
|
VMXNET3_CMD_UPDATE_VLAN_FILTERS);
|
|
|
|
}
|
2015-07-09 18:24:09 +00:00
|
|
|
}
|
|
|
|
|
2014-02-10 15:27:26 +00:00
|
|
|
#if PROCESS_SYS_EVENTS == 1
|
|
|
|
static void
|
|
|
|
vmxnet3_process_events(struct vmxnet3_hw *hw)
|
|
|
|
{
|
|
|
|
uint32_t events = hw->shared->ecr;
|
2014-06-13 01:37:04 +00:00
|
|
|
|
|
|
|
if (!events) {
|
2016-02-10 16:12:39 +00:00
|
|
|
PMD_INIT_LOG(ERR, "No events to process");
|
2014-02-10 15:27:26 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-06-03 23:42:50 +00:00
|
|
|
/*
|
2014-06-13 01:37:04 +00:00
|
|
|
* ECR bits when written with 1b are cleared. Hence write
|
|
|
|
* events back to ECR so that the bits which were set will be reset.
|
|
|
|
*/
|
2014-02-10 15:27:26 +00:00
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
|
|
|
|
|
|
|
|
/* Check if link state has changed */
|
2014-06-13 01:37:04 +00:00
|
|
|
if (events & VMXNET3_ECR_LINK)
|
|
|
|
PMD_INIT_LOG(ERR,
|
2014-06-13 01:37:13 +00:00
|
|
|
"Process events in %s(): VMXNET3_ECR_LINK event", __func__);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
/* Check if there is an error on xmit/recv queues */
|
|
|
|
if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
|
|
|
|
VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_QUEUE_STATUS);
|
|
|
|
|
|
|
|
if (hw->tqd_start->status.stopped)
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(ERR, "tq error 0x%x",
|
2014-06-13 01:37:04 +00:00
|
|
|
hw->tqd_start->status.error);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
if (hw->rqd_start->status.stopped)
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(ERR, "rq error 0x%x",
|
2014-06-13 01:37:04 +00:00
|
|
|
hw->rqd_start->status.error);
|
2014-02-10 15:27:26 +00:00
|
|
|
|
2014-06-13 01:37:04 +00:00
|
|
|
/* Reset the device */
|
|
|
|
/* Have to reset the device */
|
2014-02-10 15:27:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (events & VMXNET3_ECR_DIC)
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(ERR, "Device implementation change event.");
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
if (events & VMXNET3_ECR_DEBUG)
|
2014-06-13 01:37:13 +00:00
|
|
|
PMD_INIT_LOG(ERR, "Debug event generated by device.");
|
2014-02-10 15:27:26 +00:00
|
|
|
|
|
|
|
}
|
|
|
|
#endif
|
2014-04-21 14:59:38 +00:00
|
|
|
|
|
|
|
static struct rte_driver rte_vmxnet3_driver = {
|
|
|
|
.type = PMD_PDEV,
|
|
|
|
.init = rte_vmxnet3_pmd_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
PMD_REGISTER_DRIVER(rte_vmxnet3_driver);
|