75 lines
2.9 KiB
C
75 lines
2.9 KiB
C
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/*
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* Copyright (c) 2009-2016 Solarflare Communications Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation are
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* those of the authors and should not be interpreted as representing official
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* policies, either expressed or implied, of the FreeBSD Project.
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*/
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#include "efx.h"
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#include "efx_impl.h"
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#if EFSYS_OPT_SIENA
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void
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siena_sram_init(
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__in efx_nic_t *enp)
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{
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efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
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efx_oword_t oword;
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uint32_t rx_base, tx_base;
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EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
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EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
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rx_base = encp->enc_buftbl_limit;
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tx_base = rx_base + (encp->enc_rxq_limit *
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EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
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/* Initialize the transmit descriptor cache */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
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EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
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/* Initialize the receive descriptor cache */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
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EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
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/* Set receive descriptor pre-fetch low water mark */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
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EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
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/* Set the event queue to use for SRAM updates */
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EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
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EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
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}
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#endif /* EFSYS_OPT_SIENA */
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