183 lines
6.3 KiB
C
183 lines
6.3 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 Marvell.
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*/
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#ifndef __SDP_HW_H_
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#define __SDP_HW_H_
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/* SDP VF IOQs */
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#define SDP_MIN_RINGS_PER_VF (1)
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#define SDP_MAX_RINGS_PER_VF (8)
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/* SDP VF IQ configuration */
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#define SDP_VF_MAX_IQ_DESCRIPTORS (512)
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#define SDP_VF_MIN_IQ_DESCRIPTORS (128)
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#define SDP_VF_DB_MIN (1)
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#define SDP_VF_DB_TIMEOUT (1)
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#define SDP_VF_INTR_THRESHOLD (0xFFFFFFFF)
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#define SDP_VF_64BYTE_INSTR (64)
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#define SDP_VF_32BYTE_INSTR (32)
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/* SDP VF OQ configuration */
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#define SDP_VF_MAX_OQ_DESCRIPTORS (512)
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#define SDP_VF_MIN_OQ_DESCRIPTORS (128)
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#define SDP_VF_OQ_BUF_SIZE (2048)
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#define SDP_VF_OQ_REFIL_THRESHOLD (16)
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#define SDP_VF_OQ_INFOPTR_MODE (1)
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#define SDP_VF_OQ_BUFPTR_MODE (0)
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#define SDP_VF_OQ_INTR_PKT (1)
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#define SDP_VF_OQ_INTR_TIME (10)
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#define SDP_VF_CFG_IO_QUEUES SDP_MAX_RINGS_PER_VF
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/* Wait time in milliseconds for FLR */
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#define SDP_VF_PCI_FLR_WAIT (100)
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#define SDP_VF_BUSY_LOOP_COUNT (10000)
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#define SDP_VF_MAX_IO_QUEUES SDP_MAX_RINGS_PER_VF
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#define SDP_VF_MIN_IO_QUEUES SDP_MIN_RINGS_PER_VF
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/* SDP VF IOQs per rawdev */
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#define SDP_VF_MAX_IOQS_PER_RAWDEV SDP_VF_MAX_IO_QUEUES
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#define SDP_VF_DEFAULT_IOQS_PER_RAWDEV SDP_VF_MIN_IO_QUEUES
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/* SDP VF Register definitions */
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#define SDP_VF_RING_OFFSET (0x1ull << 17)
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/* SDP VF IQ Registers */
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#define SDP_VF_R_IN_CONTROL_START (0x10000)
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#define SDP_VF_R_IN_ENABLE_START (0x10010)
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#define SDP_VF_R_IN_INSTR_BADDR_START (0x10020)
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#define SDP_VF_R_IN_INSTR_RSIZE_START (0x10030)
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#define SDP_VF_R_IN_INSTR_DBELL_START (0x10040)
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#define SDP_VF_R_IN_CNTS_START (0x10050)
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#define SDP_VF_R_IN_INT_LEVELS_START (0x10060)
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#define SDP_VF_R_IN_PKT_CNT_START (0x10080)
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#define SDP_VF_R_IN_BYTE_CNT_START (0x10090)
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#define SDP_VF_R_IN_CONTROL(ring) \
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(SDP_VF_R_IN_CONTROL_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_ENABLE(ring) \
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(SDP_VF_R_IN_ENABLE_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_INSTR_BADDR(ring) \
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(SDP_VF_R_IN_INSTR_BADDR_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_INSTR_RSIZE(ring) \
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(SDP_VF_R_IN_INSTR_RSIZE_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_INSTR_DBELL(ring) \
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(SDP_VF_R_IN_INSTR_DBELL_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_CNTS(ring) \
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(SDP_VF_R_IN_CNTS_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_INT_LEVELS(ring) \
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(SDP_VF_R_IN_INT_LEVELS_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_PKT_CNT(ring) \
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(SDP_VF_R_IN_PKT_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_IN_BYTE_CNT(ring) \
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(SDP_VF_R_IN_BYTE_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
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/* SDP VF IQ Masks */
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#define SDP_VF_R_IN_CTL_RPVF_MASK (0xF)
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#define SDP_VF_R_IN_CTL_RPVF_POS (48)
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#define SDP_VF_R_IN_CTL_IDLE (0x1ull << 28)
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#define SDP_VF_R_IN_CTL_RDSIZE (0x3ull << 25) /* Setting to max(4) */
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#define SDP_VF_R_IN_CTL_IS_64B (0x1ull << 24)
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#define SDP_VF_R_IN_CTL_D_NSR (0x1ull << 8)
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#define SDP_VF_R_IN_CTL_D_ESR (0x1ull << 6)
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#define SDP_VF_R_IN_CTL_D_ROR (0x1ull << 5)
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#define SDP_VF_R_IN_CTL_NSR (0x1ull << 3)
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#define SDP_VF_R_IN_CTL_ESR (0x1ull << 1)
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#define SDP_VF_R_IN_CTL_ROR (0x1ull << 0)
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#define SDP_VF_R_IN_CTL_MASK (SDP_VF_R_IN_CTL_RDSIZE | SDP_VF_R_IN_CTL_IS_64B)
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/* SDP VF OQ Registers */
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#define SDP_VF_R_OUT_CNTS_START (0x10100)
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#define SDP_VF_R_OUT_INT_LEVELS_START (0x10110)
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#define SDP_VF_R_OUT_SLIST_BADDR_START (0x10120)
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#define SDP_VF_R_OUT_SLIST_RSIZE_START (0x10130)
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#define SDP_VF_R_OUT_SLIST_DBELL_START (0x10140)
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#define SDP_VF_R_OUT_CONTROL_START (0x10150)
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#define SDP_VF_R_OUT_ENABLE_START (0x10160)
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#define SDP_VF_R_OUT_PKT_CNT_START (0x10180)
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#define SDP_VF_R_OUT_BYTE_CNT_START (0x10190)
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#define SDP_VF_R_OUT_CONTROL(ring) \
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(SDP_VF_R_OUT_CONTROL_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_ENABLE(ring) \
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(SDP_VF_R_OUT_ENABLE_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_SLIST_BADDR(ring) \
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(SDP_VF_R_OUT_SLIST_BADDR_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_SLIST_RSIZE(ring) \
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(SDP_VF_R_OUT_SLIST_RSIZE_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_SLIST_DBELL(ring) \
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(SDP_VF_R_OUT_SLIST_DBELL_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_CNTS(ring) \
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(SDP_VF_R_OUT_CNTS_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_INT_LEVELS(ring) \
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(SDP_VF_R_OUT_INT_LEVELS_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_PKT_CNT(ring) \
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(SDP_VF_R_OUT_PKT_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
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#define SDP_VF_R_OUT_BYTE_CNT(ring) \
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(SDP_VF_R_OUT_BYTE_CNT_START + (SDP_VF_RING_OFFSET * (ring)))
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/* SDP VF OQ Masks */
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#define SDP_VF_R_OUT_CTL_IDLE (1ull << 40)
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#define SDP_VF_R_OUT_CTL_ES_I (1ull << 34)
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#define SDP_VF_R_OUT_CTL_NSR_I (1ull << 33)
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#define SDP_VF_R_OUT_CTL_ROR_I (1ull << 32)
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#define SDP_VF_R_OUT_CTL_ES_D (1ull << 30)
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#define SDP_VF_R_OUT_CTL_NSR_D (1ull << 29)
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#define SDP_VF_R_OUT_CTL_ROR_D (1ull << 28)
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#define SDP_VF_R_OUT_CTL_ES_P (1ull << 26)
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#define SDP_VF_R_OUT_CTL_NSR_P (1ull << 25)
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#define SDP_VF_R_OUT_CTL_ROR_P (1ull << 24)
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#define SDP_VF_R_OUT_CTL_IMODE (1ull << 23)
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#define SDP_VF_R_OUT_INT_LEVELS_BMODE (1ull << 63)
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#define SDP_VF_R_OUT_INT_LEVELS_TIMET (32)
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/* SDP Instruction Header */
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struct sdp_instr_ih {
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/* Data Len */
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uint64_t tlen : 16;
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/* Reserved1 */
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uint64_t rsvd1 : 20;
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/* PKIND for SDP */
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uint64_t pkind : 6;
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/* Front Data size */
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uint64_t fsz : 6;
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/* No. of entries in gather list */
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uint64_t gsz : 14;
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/* Gather indicator */
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uint64_t gather : 1;
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/* Reserved2 */
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uint64_t rsvd2 : 1;
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} __plt_packed;
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#endif /* __SDP_HW_H_ */
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