2017-12-19 15:49:03 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017 Intel Corporation
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2017-04-05 20:49:49 +00:00
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*/
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#include <stddef.h>
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#include <string.h>
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#include <stdint.h>
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#include <rte_cpuflags.h>
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#include <rte_common.h>
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#include <rte_net_crc.h>
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2017-06-20 15:23:02 +00:00
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#if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ)
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2017-04-05 20:49:49 +00:00
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#define X86_64_SSE42_PCLMULQDQ 1
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2017-07-04 09:24:07 +00:00
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#elif defined(RTE_ARCH_ARM64) && defined(RTE_MACHINE_CPUFLAG_PMULL)
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#define ARM64_NEON_PMULL 1
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2017-04-05 20:49:49 +00:00
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#endif
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#ifdef X86_64_SSE42_PCLMULQDQ
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#include <net_crc_sse.h>
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2017-07-04 09:24:07 +00:00
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#elif defined ARM64_NEON_PMULL
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#include <net_crc_neon.h>
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2017-04-05 20:49:49 +00:00
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#endif
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/* crc tables */
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static uint32_t crc32_eth_lut[CRC_LUT_SIZE];
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static uint32_t crc16_ccitt_lut[CRC_LUT_SIZE];
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static uint32_t
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rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len);
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static uint32_t
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rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len);
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typedef uint32_t
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(*rte_net_crc_handler)(const uint8_t *data, uint32_t data_len);
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static rte_net_crc_handler *handlers;
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static rte_net_crc_handler handlers_scalar[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_handler,
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};
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#ifdef X86_64_SSE42_PCLMULQDQ
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static rte_net_crc_handler handlers_sse42[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_sse42_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_sse42_handler,
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};
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2017-07-04 09:24:07 +00:00
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#elif defined ARM64_NEON_PMULL
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static rte_net_crc_handler handlers_neon[] = {
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[RTE_NET_CRC16_CCITT] = rte_crc16_ccitt_neon_handler,
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[RTE_NET_CRC32_ETH] = rte_crc32_eth_neon_handler,
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};
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2017-04-05 20:49:49 +00:00
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#endif
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/**
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* Reflect the bits about the middle
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*
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* @param val
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* value to be reflected
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*
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* @return
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* reflected value
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*/
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static uint32_t
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reflect_32bits(uint32_t val)
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{
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uint32_t i, res = 0;
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for (i = 0; i < 32; i++)
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2018-10-28 01:08:44 +00:00
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if ((val & (1U << i)) != 0)
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res |= (uint32_t)(1U << (31 - i));
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2017-04-05 20:49:49 +00:00
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return res;
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}
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static void
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crc32_eth_init_lut(uint32_t poly,
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uint32_t *lut)
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{
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uint32_t i, j;
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for (i = 0; i < CRC_LUT_SIZE; i++) {
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uint32_t crc = reflect_32bits(i);
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for (j = 0; j < 8; j++) {
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if (crc & 0x80000000L)
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crc = (crc << 1) ^ poly;
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else
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crc <<= 1;
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}
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lut[i] = reflect_32bits(crc);
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}
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}
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2017-05-13 09:27:25 +00:00
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static __rte_always_inline uint32_t
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2017-04-05 20:49:49 +00:00
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crc32_eth_calc_lut(const uint8_t *data,
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uint32_t data_len,
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uint32_t crc,
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const uint32_t *lut)
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{
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while (data_len--)
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crc = lut[(crc ^ *data++) & 0xffL] ^ (crc >> 8);
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return crc;
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}
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static void
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rte_net_crc_scalar_init(void)
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{
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/* 32-bit crc init */
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crc32_eth_init_lut(CRC32_ETH_POLYNOMIAL, crc32_eth_lut);
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/* 16-bit CRC init */
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crc32_eth_init_lut(CRC16_CCITT_POLYNOMIAL << 16, crc16_ccitt_lut);
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}
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static inline uint32_t
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rte_crc16_ccitt_handler(const uint8_t *data, uint32_t data_len)
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{
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/* return 16-bit CRC value */
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return (uint16_t)~crc32_eth_calc_lut(data,
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data_len,
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0xffff,
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crc16_ccitt_lut);
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}
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static inline uint32_t
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rte_crc32_eth_handler(const uint8_t *data, uint32_t data_len)
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{
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/* return 32-bit CRC value */
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return ~crc32_eth_calc_lut(data,
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data_len,
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0xffffffffUL,
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crc32_eth_lut);
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}
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void
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rte_net_crc_set_alg(enum rte_net_crc_alg alg)
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{
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switch (alg) {
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#ifdef X86_64_SSE42_PCLMULQDQ
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2017-07-04 09:24:07 +00:00
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case RTE_NET_CRC_SSE42:
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2017-04-05 20:49:49 +00:00
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handlers = handlers_sse42;
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2017-05-04 15:38:19 +00:00
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break;
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2017-07-04 09:24:07 +00:00
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#elif defined ARM64_NEON_PMULL
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/* fall-through */
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case RTE_NET_CRC_NEON:
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if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
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handlers = handlers_neon;
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break;
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}
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#endif
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/* fall-through */
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2017-04-05 20:49:49 +00:00
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case RTE_NET_CRC_SCALAR:
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2017-07-04 09:24:07 +00:00
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/* fall-through */
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2017-04-05 20:49:49 +00:00
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default:
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handlers = handlers_scalar;
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break;
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}
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}
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uint32_t
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rte_net_crc_calc(const void *data,
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uint32_t data_len,
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enum rte_net_crc_type type)
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{
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uint32_t ret;
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rte_net_crc_handler f_handle;
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f_handle = handlers[type];
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2017-04-07 17:44:47 +00:00
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ret = f_handle(data, data_len);
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2017-04-05 20:49:49 +00:00
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return ret;
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}
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/* Select highest available crc algorithm as default one */
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2017-11-02 22:06:38 +00:00
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RTE_INIT(rte_net_crc_init)
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2017-04-05 20:49:49 +00:00
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{
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enum rte_net_crc_alg alg = RTE_NET_CRC_SCALAR;
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rte_net_crc_scalar_init();
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#ifdef X86_64_SSE42_PCLMULQDQ
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2017-07-04 09:24:07 +00:00
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alg = RTE_NET_CRC_SSE42;
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rte_net_crc_sse42_init();
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#elif defined ARM64_NEON_PMULL
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if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) {
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alg = RTE_NET_CRC_NEON;
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rte_net_crc_neon_init();
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}
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2017-04-05 20:49:49 +00:00
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#endif
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rte_net_crc_set_alg(alg);
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}
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