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.. SPDX-License-Identifier: BSD-3-Clause
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Copyright 2015 6WIND S.A.
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Copyright 2015 Mellanox Technologies, Ltd
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.. include :: <isonum.txt>
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MLX5 poll mode driver
=====================
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The MLX5 poll mode driver library (**librte_net_mlx5** ) provides support
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for **Mellanox ConnectX-4** , **Mellanox ConnectX-4 Lx** , **Mellanox
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ConnectX-5**, ** Mellanox ConnectX-6**, ** Mellanox ConnectX-6 Dx**, ** Mellanox
ConnectX-6 Lx**, ** Mellanox BlueField** and ** Mellanox BlueField-2** families
of 10/25/40/50/100/200 Gb/s adapters as well as their virtual functions (VF)
in SR-IOV context.
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Information and documentation about these adapters can be found on the
`Mellanox website <http://www.mellanox.com> `__ . Help is also provided by the
`Mellanox community <http://community.mellanox.com/welcome> `__ .
There is also a `section dedicated to this poll mode driver
<http://www.mellanox.com/page/products_dyn?product_family=209&mtag=pmd_for_dpdk> `__.
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Design
------
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Besides its dependency on libibverbs (that implies libmlx5 and associated
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kernel support), librte_net_mlx5 relies heavily on system calls for control
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operations such as querying/updating the MTU and flow control parameters.
For security reasons and robustness, this driver only deals with virtual
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memory addresses. The way resources allocations are handled by the kernel,
combined with hardware specifications that allow to handle virtual memory
addresses directly, ensure that DPDK applications cannot access random
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physical memory (or memory that does not belong to the current process).
This capability allows the PMD to coexist with kernel network interfaces
which remain functional, although they stop receiving unicast packets as
long as they share the same MAC address.
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This means legacy linux control tools (for example: ethtool, ifconfig and
more) can operate on the same network interfaces that owned by the DPDK
application.
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The PMD can use libibverbs and libmlx5 to access the device firmware
or directly the hardware components.
There are different levels of objects and bypassing abilities
to get the best performances:
- Verbs is a complete high-level generic API
- Direct Verbs is a device-specific API
- DevX allows to access firmware objects
- Direct Rules manages flow steering at low-level hardware layer
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Enabling librte_net_mlx5 causes DPDK applications to be linked against
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libibverbs.
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Features
--------
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- Multi arch support: x86_64, POWER8, ARMv8, i686.
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- Multiple TX and RX queues.
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- Support for scattered TX frames.
- Advanced support for scattered Rx frames with tunable buffer attributes.
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- IPv4, IPv6, TCPv4, TCPv6, UDPv4 and UDPv6 RSS on any number of queues.
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- RSS using different combinations of fields: L3 only, L4 only or both,
and source only, destination only or both.
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- Several RSS hash keys, one for each flow type.
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- Default RSS operation with no hash key specification.
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- Configurable RETA table.
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- Link flow control (pause frame).
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- Support for multiple MAC addresses.
- VLAN filtering.
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- RX VLAN stripping.
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- TX VLAN insertion.
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- RX CRC stripping configuration.
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- Promiscuous mode on PF and VF.
- Multicast promiscuous mode on PF and VF.
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- Hardware checksum offloads.
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- Flow director (RTE_FDIR_MODE_PERFECT, RTE_FDIR_MODE_PERFECT_MAC_VLAN and
RTE_ETH_FDIR_REJECT).
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- Flow API, including :ref: `flow_isolated_mode` .
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- Multiple process.
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- KVM and VMware ESX SR-IOV modes are supported.
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- RSS hash result is supported.
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- Hardware TSO for generic IP or UDP tunnel, including VXLAN and GRE.
- Hardware checksum Tx offload for generic IP or UDP tunnel, including VXLAN and GRE.
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- RX interrupts.
- Statistics query including Basic, Extended and per queue.
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- Rx HW timestamp.
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- Tunnel types: VXLAN, L3 VXLAN, VXLAN-GPE, GRE, MPLSoGRE, MPLSoUDP, IP-in-IP, Geneve, GTP.
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- Tunnel HW offloads: packet type, inner/outer RSS, IP and UDP checksum verification.
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- NIC HW offloads: encapsulation (vxlan, gre, mplsoudp, mplsogre), NAT, routing, TTL
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increment/decrement, count, drop, mark. For details please see :ref: `mlx5_offloads_support` .
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- Flow insertion rate of more then million flows per second, when using Direct Rules.
- Support for multiple rte_flow groups.
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- Per packet no-inline hint flag to disable packet data copying into Tx descriptors.
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- Hardware LRO.
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- Hairpin.
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- Multiple-thread flow insertion.
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- Matching on GTP extension header with raw encap/decap action.
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- Matching on Geneve TLV option header with raw encap/decap action.
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- RSS support in sample action.
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Limitations
-----------
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- Windows support:
On Windows, the features are limited:
- Promiscuous mode is not supported
- The following rules are supported:
- IPv4/UDP with CVLAN filtering
- Unicast MAC filtering
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- For secondary process:
- Forked secondary process not supported.
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- External memory unregistered in EAL memseg list cannot be used for DMA
unless such memory has been registered by `` mlx5_mr_update_ext_mp() `` in
primary process and remapped to the same virtual address in secondary
process. If the external memory is registered by primary process but has
different virtual address in secondary process, unexpected error may happen.
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- When using Verbs flow engine (`` dv_flow_en `` = 0), flow pattern without any
specific VLAN will match for VLAN packets as well:
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When VLAN spec is not specified in the pattern, the matching rule will be created with VLAN as a wild card.
Meaning, the flow rule::
flow create 0 ingress pattern eth / vlan vid is 3 / ipv4 / end ...
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Will only match vlan packets with vid=3. and the flow rule::
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flow create 0 ingress pattern eth / ipv4 / end ...
Will match any ipv4 packet (VLAN included).
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- When using Verbs flow engine (`` dv_flow_en `` = 0), multi-tagged(QinQ) match is not supported.
- When using DV flow engine (`` dv_flow_en `` = 1), flow pattern with any VLAN specification will match only single-tagged packets unless the ETH item `` type `` field is 0x88A8 or the VLAN item `` has_more_vlan `` field is 1.
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The flow rule::
flow create 0 ingress pattern eth / ipv4 / end ...
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Will match any ipv4 packet.
The flow rules::
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flow create 0 ingress pattern eth / vlan / end ...
flow create 0 ingress pattern eth has_vlan is 1 / end ...
flow create 0 ingress pattern eth type is 0x8100 / end ...
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Will match single-tagged packets only, with any VLAN ID value.
The flow rules::
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flow create 0 ingress pattern eth type is 0x88A8 / end ...
flow create 0 ingress pattern eth / vlan has_more_vlan is 1 / end ...
Will match multi-tagged packets only, with any VLAN ID value.
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- A flow pattern with 2 sequential VLAN items is not supported.
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- VLAN pop offload command:
- Flow rules having a VLAN pop offload command as one of their actions and
are lacking a match on VLAN as one of their items are not supported.
- The command is not supported on egress traffic.
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- VLAN push offload is not supported on ingress traffic.
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- VLAN set PCP offload is not supported on existing headers.
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- A multi segment packet must have not more segments than reported by dev_infos_get()
in tx_desc_lim.nb_seg_max field. This value depends on maximal supported Tx descriptor
size and `` txq_inline_min `` settings and may be from 2 (worst case forced by maximal
inline settings) to 58.
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- Flows with a VXLAN Network Identifier equal (or ends to be equal)
to 0 are not supported.
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- L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP.
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- Match on Geneve header supports the following fields only:
- VNI
- OAM
- protocol type
- options length
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- Match on Geneve TLV option is supported on the following fields:
- Class
- Type
- Length
- Data
Only one Class/Type/Length Geneve TLV option is supported per shared device.
Class/Type/Length fields must be specified as well as masks.
Class/Type/Length specified masks must be full.
Matching Geneve TLV option without specifying data is not supported.
Matching Geneve TLV option with `` data & mask == 0 `` is not supported.
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- VF: flow rules created on VF devices can only match traffic targeted at the
configured MAC addresses (see `` rte_eth_dev_mac_addr_add() `` ).
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- Match on GTP tunnel header item supports the following fields only:
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- v_pt_rsv_flags: E flag, S flag, PN flag
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- msg_type
- teid
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- Match on GTP extension header only for GTP PDU session container (next
extension header type = 0x85).
- Match on GTP extension header is not supported in group 0.
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- No Tx metadata go to the E-Switch steering domain for the Flow group 0.
The flows within group 0 and set metadata action are rejected by hardware.
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.. note ::
MAC addresses not already present in the bridge table of the associated
kernel network device will be added and cleaned up by the PMD when closing
the device. In case of ungraceful program termination, some entries may
remain present and should be removed manually by other means.
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- Buffer split offload is supported with regular Rx burst routine only,
no MPRQ feature or vectorized code can be engaged.
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- When Multi-Packet Rx queue is configured (`` mprq_en `` ), a Rx packet can be
externally attached to a user-provided mbuf with having EXT_ATTACHED_MBUF in
ol_flags. As the mempool for the external buffer is managed by PMD, all the
Rx mbufs must be freed before the device is closed. Otherwise, the mempool of
the external buffers will be freed by PMD and the application which still
holds the external buffers may be corrupted.
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- If Multi-Packet Rx queue is configured (`` mprq_en `` ) and Rx CQE compression is
enabled (`` rxq_cqe_comp_en `` ) at the same time, RSS hash result is not fully
supported. Some Rx packets may not have PKT_RX_RSS_HASH.
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- IPv6 Multicast messages are not supported on VM, while promiscuous mode
and allmulticast mode are both set to off.
To receive IPv6 Multicast messages on VM, explicitly set the relevant
MAC address using rte_eth_dev_mac_addr_add() API.
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- To support a mixed traffic pattern (some buffers from local host memory, some
buffers from other devices) with high bandwidth, a mbuf flag is used.
An application hints the PMD whether or not it should try to inline the
given mbuf data buffer. PMD should do the best effort to act upon this request.
The hint flag `` RTE_PMD_MLX5_FINE_GRANULARITY_INLINE `` is dynamic,
registered by application with rte_mbuf_dynflag_register(). This flag is
purely driver-specific and declared in PMD specific header `` rte_pmd_mlx5.h `` ,
which is intended to be used by the application.
To query the supported specific flags in runtime,
the function `` rte_pmd_mlx5_get_dyn_flag_names `` returns the array of
currently (over present hardware and configuration) supported specific flags.
The "not inline hint" feature operating flow is the following one:
- application starts
- probe the devices, ports are created
- query the port capabilities
- if port supporting the feature is found
- register dynamic flag `` RTE_PMD_MLX5_FINE_GRANULARITY_INLINE ``
- application starts the ports
- on `` dev_start() `` PMD checks whether the feature flag is registered and
enables the feature support in datapath
- application might set the registered flag bit in `` ol_flags `` field
of mbuf being sent and PMD will handle ones appropriately.
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- The amount of descriptors in Tx queue may be limited by data inline settings.
Inline data require the more descriptor building blocks and overall block
amount may exceed the hardware supported limits. The application should
reduce the requested Tx size or adjust data inline settings with
`` txq_inline_max `` and `` txq_inline_mpw `` devargs keys.
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- To provide the packet send scheduling on mbuf timestamps the `` tx_pp ``
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parameter should be specified.
When PMD sees the RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME set on the packet
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being sent it tries to synchronize the time of packet appearing on
the wire with the specified packet timestamp. It the specified one
is in the past it should be ignored, if one is in the distant future
it should be capped with some reasonable value (in range of seconds).
These specific cases ("too late" and "distant future") can be optionally
reported via device xstats to assist applications to detect the
time-related problems.
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The timestamp upper "too-distant-future" limit
at the moment of invoking the Tx burst routine
can be estimated as `` tx_pp `` option (in nanoseconds) multiplied by 2^23.
Please note, for the testpmd txonly mode,
the limit is deduced from the expression::
(n_tx_descriptors / burst_size + 1) * inter_burst_gap
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There is no any packet reordering according timestamps is supposed,
neither within packet burst, nor between packets, it is an entirely
application responsibility to generate packets and its timestamps
in desired order. The timestamps can be put only in the first packet
in the burst providing the entire burst scheduling.
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- E-Switch decapsulation Flow:
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- can be applied to PF port only.
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- must specify VF port action (packet redirection from PF to VF).
- optionally may specify tunnel inner source and destination MAC addresses.
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- E-Switch encapsulation Flow:
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- can be applied to VF ports only.
- must specify PF port action (packet redirection from VF to PF).
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- Raw encapsulation:
- The input buffer, used as outer header, is not validated.
- Raw decapsulation:
- The decapsulation is always done up to the outermost tunnel detected by the HW.
- The input buffer, providing the removal size, is not validated.
- The buffer size must match the length of the headers to be removed.
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- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all
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mutually exclusive features which cannot be supported together
(see :ref: `mlx5_firmware_config` ).
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- LRO:
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- Requires DevX and DV flow to be enabled.
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- KEEP_CRC offload cannot be supported with LRO.
- The first mbuf length, without head-room, must be big enough to include the
TCP header (122B).
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- Rx queue with LRO offload enabled, receiving a non-LRO packet, can forward
it with size limited to max LRO size, not to max RX packet length.
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- LRO can be used with outer header of TCP packets of the standard format:
eth (with or without vlan) / ipv4 or ipv6 / tcp / payload
Other TCP packets (e.g. with MPLS label) received on Rx queue with LRO enabled, will be received with bad checksum.
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- LRO packet aggregation is performed by HW only for packet size larger than
`` lro_min_mss_size `` . This value is reported on device start, when debug
mode is enabled.
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- CRC:
- `` DEV_RX_OFFLOAD_KEEP_CRC `` cannot be supported with decapsulation
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for some NICs (such as ConnectX-6 Dx, ConnectX-6 Lx, and BlueField-2).
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The capability bit `` scatter_fcs_w_decap_disable `` shows NIC support.
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- Sample flow:
- Supports `` RTE_FLOW_ACTION_TYPE_SAMPLE `` action only within NIC Rx and E-Switch steering domain.
- The E-Switch Sample flow must have the eswitch_manager VPORT destination (PF or ECPF) and no additional actions.
- For ConnectX-5, the `` RTE_FLOW_ACTION_TYPE_SAMPLE `` is typically used as first action in the E-Switch egress flow if with header modify or encapsulation actions.
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- IPv6 header item 'proto' field, indicating the next header protocol, should
not be set as extension header.
In case the next header is an extension header, it should not be specified in
IPv6 header item 'proto' field.
The last extension header item 'next header' field can specify the following
header protocol type.
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- Hairpin:
- Hairpin between two ports could only manual binding and explicit Tx flow mode. For single port hairpin, all the combinations of auto/manual binding and explicit/implicit Tx flow mode could be supported.
- Hairpin in switchdev SR-IOV mode is not supported till now.
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Statistics
----------
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MLX5 supports various methods to report statistics:
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Port statistics can be queried using `` rte_eth_stats_get() `` . The received and sent statistics are through SW only and counts the number of packets received or sent successfully by the PMD. The imissed counter is the amount of packets that could not be delivered to SW because a queue was full. Packets not received due to congestion in the bus or on the NIC can be queried via the rx_discards_phy xstats counter.
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Extended statistics can be queried using `` rte_eth_xstats_get() `` . The extended statistics expose a wider set of counters counted by the device. The extended port statistics counts the number of packets received or sent successfully by the port. As Mellanox NICs are using the :ref: `Bifurcated Linux Driver <linux_gsg_linux_drivers>` those counters counts also packet received or sent by the Linux kernel. The counters with `` _phy `` suffix counts the total events on the physical port, therefore not valid for VF.
Finally per-flow statistics can by queried using `` rte_flow_query `` when attaching a count action for specific flow. The flow counter counts the number of packets received successfully by the port and match the specific flow.
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Configuration
-------------
Compilation options
~~~~~~~~~~~~~~~~~~~
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The ibverbs libraries can be linked with this PMD in a number of ways,
configured by the `` ibverbs_link `` build option:
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- `` shared `` (default): the PMD depends on some .so files.
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- `` dlopen `` : Split the dependencies glue in a separate library
loaded when needed by dlopen.
It make dependencies on libibverbs and libmlx4 optional,
and has no performance impact.
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- `` static `` : Embed static flavor of the dependencies libibverbs and libmlx4
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in the PMD shared library or the executable static binary.
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Environment variables
~~~~~~~~~~~~~~~~~~~~~
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- `` MLX5_GLUE_PATH ``
A list of directories in which to search for the rdma-core "glue" plug-in,
separated by colons or semi-colons.
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- `` MLX5_SHUT_UP_BF ``
Configures HW Tx doorbell register as IO-mapped.
By default, the HW Tx doorbell is configured as a write-combining register.
The register would be flushed to HW usually when the write-combining buffer
becomes full, but it depends on CPU design.
Except for vectorized Tx burst routines, a write memory barrier is enforced
after updating the register so that the update can be immediately visible to
HW.
When vectorized Tx burst is called, the barrier is set only if the burst size
is not aligned to MLX5_VPMD_TX_MAX_BURST. However, setting this environmental
variable will bring better latency even though the maximum throughput can
slightly decline.
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Run-time configuration
~~~~~~~~~~~~~~~~~~~~~~
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- librte_net_mlx5 brings kernel network interfaces up during initialization
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because it is affected by their state. Forcing them down prevents packets
reception.
- **ethtool** operations on related kernel interfaces also affect the PMD.
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Run as non-root
^^^^^^^^^^^^^^^
In order to run as a non-root user,
some capabilities must be granted to the application::
setcap cap_sys_admin,cap_net_admin,cap_net_raw,cap_ipc_lock+ep <dpdk-app>
Below are the reasons of the need for each capability:
`` cap_sys_admin ``
When using physical addresses (PA mode), with Linux >= 4.0,
for access to `` /proc/self/pagemap `` .
`` cap_net_admin ``
For device configuration.
`` cap_net_raw ``
For raw ethernet queue allocation through kernel driver.
`` cap_ipc_lock ``
For DMA memory pinning.
Driver options
^^^^^^^^^^^^^^
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- `` rxq_cqe_comp_en `` parameter [int]
A nonzero value enables the compression of CQE on RX side. This feature
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allows to save PCI bandwidth and improve performance. Enabled by default.
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Different compression formats are supported in order to achieve the best
performance for different traffic patterns. Hash RSS format is the default.
Specifying 2 as a `` rxq_cqe_comp_en `` value selects Flow Tag format for
better compression rate in case of RTE Flow Mark traffic.
Specifying 3 as a `` rxq_cqe_comp_en `` value selects Checksum format.
Specifying 4 as a `` rxq_cqe_comp_en `` value selects L3/L4 Header format for
better compression rate in case of mixed TCP/UDP and IPv4/IPv6 traffic.
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Supported on:
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- x86_64 with ConnectX-4, ConnectX-4 Lx, ConnectX-5, ConnectX-6, ConnectX-6 Dx,
ConnectX-6 Lx, BlueField and BlueField-2.
- POWER9 and ARMv8 with ConnectX-4 Lx, ConnectX-5, ConnectX-6, ConnectX-6 Dx,
ConnectX-6 Lx, BlueField and BlueField-2.
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- `` rxq_pkt_pad_en `` parameter [int]
A nonzero value enables padding Rx packet to the size of cacheline on PCI
transaction. This feature would waste PCI bandwidth but could improve
performance by avoiding partial cacheline write which may cause costly
read-modify-copy in memory transaction on some architectures. Disabled by
default.
Supported on:
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- x86_64 with ConnectX-4, ConnectX-4 Lx, ConnectX-5, ConnectX-6, ConnectX-6 Dx,
ConnectX-6 Lx, BlueField and BlueField-2.
- POWER8 and ARMv8 with ConnectX-4 Lx, ConnectX-5, ConnectX-6, ConnectX-6 Dx,
ConnectX-6 Lx, BlueField and BlueField-2.
2019-01-15 17:38:58 +00:00
2018-05-09 11:13:50 +00:00
- `` mprq_en `` parameter [int]
A nonzero value enables configuring Multi-Packet Rx queues. Rx queue is
configured as Multi-Packet RQ if the total number of Rx queues is
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`` rxqs_min_mprq `` or more. Disabled by default.
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Multi-Packet Rx Queue (MPRQ a.k.a Striding RQ) can further save PCIe bandwidth
by posting a single large buffer for multiple packets. Instead of posting a
buffers per a packet, one large buffer is posted in order to receive multiple
packets on the buffer. A MPRQ buffer consists of multiple fixed-size strides
and each stride receives one packet. MPRQ can improve throughput for
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small-packet traffic.
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When MPRQ is enabled, max_rx_pkt_len can be larger than the size of
user-provided mbuf even if DEV_RX_OFFLOAD_SCATTER isn't enabled. PMD will
configure large stride size enough to accommodate max_rx_pkt_len as long as
device allows. Note that this can waste system memory compared to enabling Rx
scatter and multi-segment packet.
- `` mprq_log_stride_num `` parameter [int]
Log 2 of the number of strides for Multi-Packet Rx queue. Configuring more
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strides can reduce PCIe traffic further. If configured value is not in the
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range of device capability, the default value will be set with a warning
message. The default value is 4 which is 16 strides per a buffer, valid only
if `` mprq_en `` is set.
The size of Rx queue should be bigger than the number of strides.
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- `` mprq_log_stride_size `` parameter [int]
Log 2 of the size of a stride for Multi-Packet Rx queue. Configuring a smaller
stride size can save some memory and reduce probability of a depletion of all
available strides due to unreleased packets by an application. If configured
value is not in the range of device capability, the default value will be set
with a warning message. The default value is 11 which is 2048 bytes per a
stride, valid only if `` mprq_en `` is set. With `` mprq_log_stride_size `` set
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it is possible for a packet to span across multiple strides. This mode allows
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support of jumbo frames (9K) with MPRQ. The memcopy of some packets (or part
of a packet if Rx scatter is configured) may be required in case there is no
space left for a head room at the end of a stride which incurs some
performance penalty.
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- `` mprq_max_memcpy_len `` parameter [int]
The maximum length of packet to memcpy in case of Multi-Packet Rx queue. Rx
packet is mem-copied to a user-provided mbuf if the size of Rx packet is less
than or equal to this parameter. Otherwise, PMD will attach the Rx packet to
the mbuf by external buffer attachment - `` rte_pktmbuf_attach_extbuf() `` .
A mempool for external buffers will be allocated and managed by PMD. If Rx
packet is externally attached, ol_flags field of the mbuf will have
EXT_ATTACHED_MBUF and this flag must be preserved. `` RTE_MBUF_HAS_EXTBUF() ``
checks the flag. The default value is 128, valid only if `` mprq_en `` is set.
- `` rxqs_min_mprq `` parameter [int]
Configure Rx queues as Multi-Packet RQ if the total number of Rx queues is
greater or equal to this value. The default value is 12, valid only if
`` mprq_en `` is set.
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- `` txq_inline `` parameter [int]
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Amount of data to be inlined during TX operations. This parameter is
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deprecated and converted to the new parameter `` txq_inline_max `` providing
partial compatibility.
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- `` txqs_min_inline `` parameter [int]
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Enable inline data send only when the number of TX queues is greater or equal
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to this value.
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This option should be used in combination with `` txq_inline_max `` and
`` txq_inline_mpw `` below and does not affect `` txq_inline_min `` settings above.
If this option is not specified the default value 16 is used for BlueField
and 8 for other platforms
The data inlining consumes the CPU cycles, so this option is intended to
auto enable inline data if we have enough Tx queues, which means we have
enough CPU cores and PCI bandwidth is getting more critical and CPU
is not supposed to be bottleneck anymore.
The copying data into WQE improves latency and can improve PPS performance
when PCI back pressure is detected and may be useful for scenarios involving
heavy traffic on many queues.
Because additional software logic is necessary to handle this mode, this
option should be used with care, as it may lower performance when back
pressure is not expected.
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If inline data are enabled it may affect the maximal size of Tx queue in
descriptors because the inline data increase the descriptor size and
queue size limits supported by hardware may be exceeded.
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- `` txq_inline_min `` parameter [int]
Minimal amount of data to be inlined into WQE during Tx operations. NICs
may require this minimal data amount to operate correctly. The exact value
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may depend on NIC operation mode, requested offloads, etc. It is strongly
recommended to omit this parameter and use the default values. Anyway,
applications using this parameter should take into consideration that
specifying an inconsistent value may prevent the NIC from sending packets.
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If `` txq_inline_min `` key is present the specified value (may be aligned
by the driver in order not to exceed the limits and provide better descriptor
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space utilization) will be used by the driver and it is guaranteed that
requested amount of data bytes are inlined into the WQE beside other inline
settings. This key also may update `` txq_inline_max `` value (default
or specified explicitly in devargs) to reserve the space for inline data.
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If `` txq_inline_min `` key is not present, the value may be queried by the
driver from the NIC via DevX if this feature is available. If there is no DevX
enabled/supported the value 18 (supposing L2 header including VLAN) is set
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for ConnectX-4 and ConnectX-4 Lx, and 0 is set by default for ConnectX-5
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and newer NICs. If packet is shorter the `` txq_inline_min `` value, the entire
packet is inlined.
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For ConnectX-4 NIC, driver does not allow specifying value below 18
(minimal L2 header, including VLAN), error will be raised.
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For ConnectX-4 Lx NIC, it is allowed to specify values below 18, but
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it is not recommended and may prevent NIC from sending packets over
some configurations.
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Please, note, this minimal data inlining disengages eMPW feature (Enhanced
Multi-Packet Write), because last one does not support partial packet inlining.
This is not very critical due to minimal data inlining is mostly required
by ConnectX-4 and ConnectX-4 Lx, these NICs do not support eMPW feature.
- `` txq_inline_max `` parameter [int]
Specifies the maximal packet length to be completely inlined into WQE
Ethernet Segment for ordinary SEND method. If packet is larger than specified
value, the packet data won't be copied by the driver at all, data buffer
is addressed with a pointer. If packet length is less or equal all packet
data will be copied into WQE. This may improve PCI bandwidth utilization for
short packets significantly but requires the extra CPU cycles.
The data inline feature is controlled by number of Tx queues, if number of Tx
queues is larger than `` txqs_min_inline `` key parameter, the inline feature
is engaged, if there are not enough Tx queues (which means not enough CPU cores
and CPU resources are scarce), data inline is not performed by the driver.
Assigning `` txqs_min_inline `` with zero always enables the data inline.
The default `` txq_inline_max `` value is 290. The specified value may be adjusted
by the driver in order not to exceed the limit (930 bytes) and to provide better
WQE space filling without gaps, the adjustment is reflected in the debug log.
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Also, the default value (290) may be decreased in run-time if the large transmit
queue size is requested and hardware does not support enough descriptor
amount, in this case warning is emitted. If `` txq_inline_max `` key is
specified and requested inline settings can not be satisfied then error
will be raised.
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- `` txq_inline_mpw `` parameter [int]
Specifies the maximal packet length to be completely inlined into WQE for
Enhanced MPW method. If packet is large the specified value, the packet data
won't be copied, and data buffer is addressed with pointer. If packet length
is less or equal, all packet data will be copied into WQE. This may improve PCI
bandwidth utilization for short packets significantly but requires the extra
CPU cycles.
The data inline feature is controlled by number of TX queues, if number of Tx
queues is larger than `` txqs_min_inline `` key parameter, the inline feature
is engaged, if there are not enough Tx queues (which means not enough CPU cores
and CPU resources are scarce), data inline is not performed by the driver.
Assigning `` txqs_min_inline `` with zero always enables the data inline.
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The default `` txq_inline_mpw `` value is 268. The specified value may be adjusted
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by the driver in order not to exceed the limit (930 bytes) and to provide better
WQE space filling without gaps, the adjustment is reflected in the debug log.
Due to multiple packets may be included to the same WQE with Enhanced Multi
Packet Write Method and overall WQE size is limited it is not recommended to
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specify large values for the `` txq_inline_mpw `` . Also, the default value (268)
may be decreased in run-time if the large transmit queue size is requested
and hardware does not support enough descriptor amount, in this case warning
is emitted. If `` txq_inline_mpw `` key is specified and requested inline
settings can not be satisfied then error will be raised.
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- `` txqs_max_vec `` parameter [int]
Enable vectorized Tx only when the number of TX queues is less than or
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equal to this value. This parameter is deprecated and ignored, kept
for compatibility issue to not prevent driver from probing.
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- `` txq_mpw_hdr_dseg_en `` parameter [int]
A nonzero value enables including two pointers in the first block of TX
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descriptor. The parameter is deprecated and ignored, kept for compatibility
issue.
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- `` txq_max_inline_len `` parameter [int]
Maximum size of packet to be inlined. This limits the size of packet to
be inlined. If the size of a packet is larger than configured value, the
packet isn't inlined even though there's enough space remained in the
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descriptor. Instead, the packet is included with pointer. This parameter
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is deprecated and converted directly to `` txq_inline_mpw `` providing full
compatibility. Valid only if eMPW feature is engaged.
- `` txq_mpw_en `` parameter [int]
A nonzero value enables Enhanced Multi-Packet Write (eMPW) for ConnectX-5,
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ConnectX-6, ConnectX-6 Dx, ConnectX-6 Lx, BlueField, BlueField-2.
eMPW allows the Tx burst function to pack up multiple packets
in a single descriptor session in order to save PCI bandwidth
and improve performance at the cost of a slightly higher CPU usage.
When `` txq_inline_mpw `` is set along with `` txq_mpw_en `` ,
Tx burst function copies entire packet data on to Tx descriptor
instead of including pointer of packet.
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The Enhanced Multi-Packet Write feature is enabled by default if NIC supports
it, can be disabled by explicit specifying 0 value for `` txq_mpw_en `` option.
Also, if minimal data inlining is requested by non-zero `` txq_inline_min ``
option or reported by the NIC, the eMPW feature is disengaged.
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- `` tx_db_nc `` parameter [int]
The rdma core library can map doorbell register in two ways, depending on the
environment variable "MLX5_SHUT_UP_BF":
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- As regular cached memory (usually with write combining attribute), if the
variable is either missing or set to zero.
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- As non-cached memory, if the variable is present and set to not "0" value.
The type of mapping may slightly affect the Tx performance, the optimal choice
is strongly relied on the host architecture and should be deduced practically.
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If `` tx_db_nc `` is set to zero, the doorbell is forced to be mapped to regular
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memory (with write combining), the PMD will perform the extra write memory barrier
after writing to doorbell, it might increase the needed CPU clocks per packet
to send, but latency might be improved.
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If `` tx_db_nc `` is set to one, the doorbell is forced to be mapped to non
cached memory, the PMD will not perform the extra write memory barrier
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after writing to doorbell, on some architectures it might improve the
performance.
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If `` tx_db_nc `` is set to two, the doorbell is forced to be mapped to regular
memory, the PMD will use heuristics to decide whether write memory barrier
should be performed. For bursts with size multiple of recommended one (64 pkts)
it is supposed the next burst is coming and no need to issue the extra memory
barrier (it is supposed to be issued in the next coming burst, at least after
descriptor writing). It might increase latency (on some hosts till next
packets transmit) and should be used with care.
If `` tx_db_nc `` is omitted or set to zero, the preset (if any) environment
variable "MLX5_SHUT_UP_BF" value is used. If there is no "MLX5_SHUT_UP_BF",
the default `` tx_db_nc `` value is zero for ARM64 hosts and one for others.
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2020-07-16 08:23:05 +00:00
- `` tx_pp `` parameter [int]
If a nonzero value is specified the driver creates all necessary internal
objects to provide accurate packet send scheduling on mbuf timestamps.
The positive value specifies the scheduling granularity in nanoseconds,
the packet send will be accurate up to specified digits. The allowed range is
from 500 to 1 million of nanoseconds. The negative value specifies the module
of granularity and engages the special test mode the check the schedule rate.
By default (if the `` tx_pp `` is not specified) send scheduling on timestamps
feature is disabled.
- `` tx_skew `` parameter [int]
The parameter adjusts the send packet scheduling on timestamps and represents
the average delay between beginning of the transmitting descriptor processing
by the hardware and appearance of actual packet data on the wire. The value
should be provided in nanoseconds and is valid only if `` tx_pp `` parameter is
specified. The default value is zero.
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- `` tx_vec_en `` parameter [int]
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A nonzero value enables Tx vector on ConnectX-5, ConnectX-6, ConnectX-6 Dx,
ConnectX-6 Lx, BlueField and BlueField-2 NICs
if the number of global Tx queues on the port is less than `` txqs_max_vec `` .
The parameter is deprecated and ignored.
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- `` rx_vec_en `` parameter [int]
A nonzero value enables Rx vector if the port is not configured in
multi-segment otherwise this parameter is ignored.
Enabled by default.
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- `` vf_nl_en `` parameter [int]
A nonzero value enables Netlink requests from the VF to add/remove MAC
addresses or/and enable/disable promiscuous/all multicast on the Netdevice.
Otherwise the relevant configuration must be run with Linux iproute2 tools.
This is a prerequisite to receive this kind of traffic.
Enabled by default, valid only on VF devices ignored otherwise.
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- `` l3_vxlan_en `` parameter [int]
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A nonzero value allows L3 VXLAN and VXLAN-GPE flow creation. To enable
L3 VXLAN or VXLAN-GPE, users has to configure firmware and enable this
parameter. This is a prerequisite to receive this kind of traffic.
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Disabled by default.
net/mlx5: add devarg for extensive metadata support
The PMD parameter dv_xmeta_en is added to control extensive
metadata support. A nonzero value enables extensive flow
metadata support if device is capable and driver supports it.
This can enable extensive support of MARK and META item of
rte_flow. The newly introduced SET_TAG and SET_META actions
do not depend on dv_xmeta_en parameter, because there is
no compatibility issue for new entities. The dv_xmeta_en is
disabled by default.
There are some possible configurations, depending on parameter
value:
- 0, this is default value, defines the legacy mode, the MARK
and META related actions and items operate only within NIC Tx
and NIC Rx steering domains, no MARK and META information
crosses the domain boundaries. The MARK item is 24 bits wide,
the META item is 32 bits wide.
- 1, this engages extensive metadata mode, the MARK and META
related actions and items operate within all supported steering
domains, including FDB, MARK and META information may cross
the domain boundaries. The ``MARK`` item is 24 bits wide, the
META item width depends on kernel and firmware configurations
and might be 0, 16 or 32 bits. Within NIC Tx domain META data
width is 32 bits for compatibility, the actual width of data
transferred to the FDB domain depends on kernel configuration
and may be vary. The actual supported width can be retrieved
in runtime by series of rte_flow_validate() trials.
- 2, this engages extensive metadata mode, the MARK and META
related actions and items operate within all supported steering
domains, including FDB, MARK and META information may cross
the domain boundaries. The META item is 32 bits wide, the MARK
item width depends on kernel and firmware configurations and
might be 0, 16 or 24 bits. The actual supported width can be
retrieved in runtime by series of rte_flow_validate() trials.
If there is no E-Switch configuration the ``dv_xmeta_en`` parameter is
ignored and the device is configured to operate in legacy mode (0).
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-07 17:09:54 +00:00
- `` dv_xmeta_en `` parameter [int]
A nonzero value enables extensive flow metadata support if device is
capable and driver supports it. This can enable extensive support of
`` MARK `` and `` META `` item of `` rte_flow `` . The newly introduced
`` SET_TAG `` and `` SET_META `` actions do not depend on `` dv_xmeta_en `` .
There are some possible configurations, depending on parameter value:
- 0, this is default value, defines the legacy mode, the `` MARK `` and
`` META `` related actions and items operate only within NIC Tx and
NIC Rx steering domains, no `` MARK `` and `` META `` information crosses
the domain boundaries. The `` MARK `` item is 24 bits wide, the `` META ``
item is 32 bits wide and match supported on egress only.
- 1, this engages extensive metadata mode, the `` MARK `` and `` META ``
related actions and items operate within all supported steering domains,
including FDB, `` MARK `` and `` META `` information may cross the domain
boundaries. The `` MARK `` item is 24 bits wide, the `` META `` item width
depends on kernel and firmware configurations and might be 0, 16 or
32 bits. Within NIC Tx domain `` META `` data width is 32 bits for
compatibility, the actual width of data transferred to the FDB domain
depends on kernel configuration and may be vary. The actual supported
width can be retrieved in runtime by series of rte_flow_validate()
trials.
- 2, this engages extensive metadata mode, the `` MARK `` and `` META ``
related actions and items operate within all supported steering domains,
including FDB, `` MARK `` and `` META `` information may cross the domain
boundaries. The `` META `` item is 32 bits wide, the `` MARK `` item width
depends on kernel and firmware configurations and might be 0, 16 or
24 bits. The actual supported width can be retrieved in runtime by
series of rte_flow_validate() trials.
2020-10-25 14:08:09 +00:00
- 3, this engages tunnel offload mode. In E-Switch configuration, that
mode implicitly activates `` dv_xmeta_en=1 `` .
net/mlx5: add devarg for extensive metadata support
The PMD parameter dv_xmeta_en is added to control extensive
metadata support. A nonzero value enables extensive flow
metadata support if device is capable and driver supports it.
This can enable extensive support of MARK and META item of
rte_flow. The newly introduced SET_TAG and SET_META actions
do not depend on dv_xmeta_en parameter, because there is
no compatibility issue for new entities. The dv_xmeta_en is
disabled by default.
There are some possible configurations, depending on parameter
value:
- 0, this is default value, defines the legacy mode, the MARK
and META related actions and items operate only within NIC Tx
and NIC Rx steering domains, no MARK and META information
crosses the domain boundaries. The MARK item is 24 bits wide,
the META item is 32 bits wide.
- 1, this engages extensive metadata mode, the MARK and META
related actions and items operate within all supported steering
domains, including FDB, MARK and META information may cross
the domain boundaries. The ``MARK`` item is 24 bits wide, the
META item width depends on kernel and firmware configurations
and might be 0, 16 or 32 bits. Within NIC Tx domain META data
width is 32 bits for compatibility, the actual width of data
transferred to the FDB domain depends on kernel configuration
and may be vary. The actual supported width can be retrieved
in runtime by series of rte_flow_validate() trials.
- 2, this engages extensive metadata mode, the MARK and META
related actions and items operate within all supported steering
domains, including FDB, MARK and META information may cross
the domain boundaries. The META item is 32 bits wide, the MARK
item width depends on kernel and firmware configurations and
might be 0, 16 or 24 bits. The actual supported width can be
retrieved in runtime by series of rte_flow_validate() trials.
If there is no E-Switch configuration the ``dv_xmeta_en`` parameter is
ignored and the device is configured to operate in legacy mode (0).
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2019-11-07 17:09:54 +00:00
+------+-----------+-----------+-------------+-------------+
| Mode | `` MARK `` | `` META `` | `` META `` Tx | FDB/Through |
+======+===========+===========+=============+=============+
| 0 | 24 bits | 32 bits | 32 bits | no |
+------+-----------+-----------+-------------+-------------+
| 1 | 24 bits | vary 0-32 | 32 bits | yes |
+------+-----------+-----------+-------------+-------------+
| 2 | vary 0-32 | 32 bits | 32 bits | yes |
+------+-----------+-----------+-------------+-------------+
If there is no E-Switch configuration the `` dv_xmeta_en `` parameter is
ignored and the device is configured to operate in legacy mode (0).
Disabled by default (set to 0).
2019-11-18 11:20:34 +00:00
The Direct Verbs/Rules (engaged with `` dv_flow_en `` = 1) supports all
of the extensive metadata features. The legacy Verbs supports FLAG and
MARK metadata actions over NIC Rx steering domain only.
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- `` dv_flow_en `` parameter [int]
A nonzero value enables the DV flow steering assuming it is supported
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by the driver (RDMA Core library version is rdma-core-24.0 or higher).
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2019-10-24 12:52:53 +00:00
Enabled by default if supported.
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2019-05-13 11:41:02 +00:00
- `` dv_esw_en `` parameter [int]
A nonzero value enables E-Switch using Direct Rules.
Enabled by default if supported.
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- `` lacp_by_user `` parameter [int]
A nonzero value enables the control of LACP traffic by the user application.
When a bond exists in the driver, by default it should be managed by the
kernel and therefore LACP traffic should be steered to the kernel.
If this devarg is set to 1 it will allow the user to manage the bond by
itself and not steer LACP traffic to the kernel.
Disabled by default (set to 0).
2019-04-01 21:17:54 +00:00
- `` mr_ext_memseg_en `` parameter [int]
A nonzero value enables extending memseg when registering DMA memory. If
enabled, the number of entries in MR (Memory Region) lookup table on datapath
is minimized and it benefits performance. On the other hand, it worsens memory
utilization because registered memory is pinned by kernel driver. Even if a
page in the extended chunk is freed, that doesn't become reusable until the
entire memory is freed.
Enabled by default.
2018-07-10 16:04:58 +00:00
- `` representor `` parameter [list]
This parameter can be used to instantiate DPDK Ethernet devices from
existing port (or VF) representors configured on the device.
It is a standard parameter whose format is described in
:ref: `ethernet_device_standard_device_arguments` .
For instance, to probe port representors 0 through 2::
representor=[0-2]
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- `` max_dump_files_num `` parameter [int]
The maximum number of files per PMD entity that may be created for debug information.
The files will be created in /var/log directory or in current directory.
set to 128 by default.
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- `` lro_timeout_usec `` parameter [int]
The maximum allowed duration of an LRO session, in micro-seconds.
PMD will set the nearest value supported by HW, which is not bigger than
the input `` lro_timeout_usec `` value.
If this parameter is not specified, by default PMD will set
the smallest value supported by HW.
2020-04-22 03:11:20 +00:00
- `` hp_buf_log_sz `` parameter [int]
The total data buffer size of a hairpin queue (logarithmic form), in bytes.
PMD will set the data buffer size to 2 ** `` hp_buf_log_sz `` , both for RX & TX.
The capacity of the value is specified by the firmware and the initialization
will get a failure if it is out of scope.
The range of the value is from 11 to 19 right now, and the supported frame
size of a single packet for hairpin is from 512B to 128KB. It might change if
different firmware release is being used. By using a small value, it could
reduce memory consumption but not work with a large frame. If the value is
too large, the memory consumption will be high and some potential performance
degradation will be introduced.
By default, the PMD will set this value to 16, which means that 9KB jumbo
frames will be supported.
net/mlx5: add reclaim memory mode
Currently, when flow destroyed, some memory resources may still be kept
as cached to help next time create flow more efficiently.
Some system may need the resources to be more flexible with flow create
and destroy. After peak time, with millions of flows destroyed, the
system would prefer the resources to be reclaimed completely, no cache
is needed. Then the resources can be allocated and used by other
components. The system is not so sensitive about the flow insertion
rate, but more care about the resources.
Both DPDK mlx5 PMD driver and the low level component rdma-core have
provided the flow resources to be configured cached or not, but there is
no APIs or parameters exposed to user to configure the flow resources
cache mode. In this case, introduce a new PMD devarg to let user
configure the flow resources cache mode will be helpful.
This commit is to add a new "reclaim_mem_mode" to help user configure if
the destroyed flows' cache resources should be kept or not.
Their will be three mode can be chosen:
1. 0(none). It means the flow resources will be cached as usual. The
resources will be cached, helpful with flow insertion rate.
2. 1(light). It will only enable the DPDK PMD level resources reclaim.
3. 2(aggressive). Both DPDK PMD level and rdma-core low level will be
configured as reclaimed mode.
With these three mode, user can configure the resources cache mode with
different levels.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2020-06-01 06:09:43 +00:00
- `` reclaim_mem_mode `` parameter [int]
Cache some resources in flow destroy will help flow recreation more efficient.
While some systems may require the all the resources can be reclaimed after
flow destroyed.
The parameter `` reclaim_mem_mode `` provides the option for user to configure
if the resource cache is needed or not.
There are three options to choose:
- 0. It means the flow resources will be cached as usual. The resources will
be cached, helpful with flow insertion rate.
- 1. It will only enable the DPDK PMD level resources reclaim.
- 2. Both DPDK PMD level and rdma-core low level will be configured as
reclaimed mode.
By default, the PMD will set this value to 0.
net/mlx5: add option to allocate memory from system
Currently, for MLX5 PMD, once millions of flows created, the memory
consumption of the flows are also very huge. For the system with limited
memory, it means the system need to reserve most of the memory as huge
page memory to serve the flows in advance. And other normal applications
will have no chance to use this reserved memory any more. While most of
the time, the system will not have lots of flows, the reserved huge
page memory becomes a bit waste of memory at most of the time.
By the new sys_mem_en devarg, once set it to be true, it allows the PMD
allocate the memory from system by default with the new add mlx5 memory
management functions. Only once the MLX5_MEM_RTE flag is set, the memory
will be allocate from rte, otherwise, it allocates memory from system.
So in this case, the system with limited memory no need to reserve most
of the memory for hugepage. Only some needed memory for datapath objects
will be enough to allocated with explicitly flag. Other memory will be
allocated from system. For system with enough memory, no need to care
about the devarg, the memory will always be from rte hugepage.
One restriction is that for DPDK application with multiple PCI devices,
if the sys_mem_en devargs are different between the devices, the
sys_mem_en only gets the value from the first device devargs, and print
out a message to warn that.
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2020-06-28 03:41:57 +00:00
- `` sys_mem_en `` parameter [int]
A non-zero value enables the PMD memory management allocating memory
from system by default, without explicit rte memory flag.
By default, the PMD will set this value to 0.
2020-07-15 13:10:21 +00:00
- `` decap_en `` parameter [int]
Some devices do not support FCS (frame checksum) scattering for
tunnel-decapsulated packets.
If set to 0, this option forces the FCS feature and rejects tunnel
decapsulation in the flow engine for such devices.
By default, the PMD will set this value to 1.
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.. _mlx5_firmware_config:
2018-04-23 12:33:02 +00:00
Firmware configuration
~~~~~~~~~~~~~~~~~~~~~~
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Firmware features can be configured as key/value pairs.
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The command to set a value is::
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mlxconfig -d <device> set <key>=<value>
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The command to query a value is::
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mlxconfig -d <device> query | grep <key>
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The device name for the command `` mlxconfig `` can be either the PCI address,
or the mst device name found with::
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2019-08-05 15:32:18 +00:00
mst status
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Below are some firmware configurations listed.
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- link type::
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LINK_TYPE_P1
LINK_TYPE_P2
value: 1=Infiniband 2=Ethernet 3=VPI(auto-sense)
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2019-08-05 15:32:18 +00:00
- enable SR-IOV::
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2019-08-05 15:32:18 +00:00
SRIOV_EN=1
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2019-08-05 15:32:18 +00:00
- maximum number of SR-IOV virtual functions::
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2019-08-05 15:32:18 +00:00
NUM_OF_VFS=<max>
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2019-08-05 15:32:22 +00:00
- enable DevX (required by Direct Rules and other features)::
UCTX_EN=1
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- aggressive CQE zipping::
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2019-08-05 15:32:18 +00:00
CQE_COMPRESSION=1
2019-07-10 14:59:45 +00:00
2019-08-05 15:32:18 +00:00
- L3 VXLAN and VXLAN-GPE destination UDP port::
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IP_OVER_VXLAN_EN=1
IP_OVER_VXLAN_PORT=<udp dport>
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- enable VXLAN-GPE tunnel flow matching::
FLEX_PARSER_PROFILE_ENABLE=0
or
FLEX_PARSER_PROFILE_ENABLE=2
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- enable IP-in-IP tunnel flow matching::
FLEX_PARSER_PROFILE_ENABLE=0
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- enable MPLS flow matching::
FLEX_PARSER_PROFILE_ENABLE=1
2020-10-09 06:11:42 +00:00
- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching::
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FLEX_PARSER_PROFILE_ENABLE=2
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2019-10-16 08:36:10 +00:00
- enable Geneve flow matching::
FLEX_PARSER_PROFILE_ENABLE=0
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or
FLEX_PARSER_PROFILE_ENABLE=1
2019-10-16 08:36:10 +00:00
2021-01-17 10:21:22 +00:00
- enable Geneve TLV option flow matching::
FLEX_PARSER_PROFILE_ENABLE=0
2020-01-16 18:36:23 +00:00
- enable GTP flow matching::
FLEX_PARSER_PROFILE_ENABLE=3
2020-07-17 07:11:51 +00:00
- enable eCPRI flow matching::
FLEX_PARSER_PROFILE_ENABLE=4
PROG_PARSE_GRAPH=1
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Linux Prerequisites
-------------------
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This driver relies on external libraries and kernel drivers for resources
allocations and initialization. The following dependencies are not part of
DPDK and must be installed separately:
- **libibverbs**
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User space Verbs framework used by librte_net_mlx5. This library provides
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a generic interface between the kernel and low-level user space drivers
such as libmlx5.
It allows slow and privileged operations (context initialization, hardware
resources allocations) to be managed by the kernel and fast operations to
never leave user space.
- **libmlx5**
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Low-level user space driver library for Mellanox
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ConnectX-4/ConnectX-5/ConnectX-6/BlueField devices, it is automatically loaded
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by libibverbs.
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This library basically implements send/receive calls to the hardware
queues.
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- **Kernel modules**
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They provide the kernel-side Verbs API and low level device drivers that
manage actual hardware initialization and resources sharing with user
space processes.
Unlike most other PMDs, these modules must remain loaded and bound to
their devices:
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- mlx5_core: hardware driver managing Mellanox
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ConnectX-4/ConnectX-5/ConnectX-6/BlueField devices and related Ethernet kernel
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network devices.
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- mlx5_ib: InifiniBand device driver.
- ib_uverbs: user space driver for Verbs (entry point for libibverbs).
- **Firmware update**
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Mellanox OFED/EN releases include firmware updates for
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ConnectX-4/ConnectX-5/ConnectX-6/BlueField adapters.
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Because each release provides new features, these updates must be applied to
match the kernel modules and libraries they come with.
.. note ::
Both libraries are BSD and GPL licensed. Linux kernel modules are GPL
licensed.
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Installation
~~~~~~~~~~~~
2015-10-30 18:55:19 +00:00
2017-09-26 15:38:24 +00:00
Either RDMA Core library with a recent enough Linux kernel release
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(recommended) or Mellanox OFED/EN, which provides compatibility with older
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releases.
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RDMA Core with Linux Kernel
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- Minimal kernel version : v4.14 or the most recent 4.14-rc (see `Linux installation documentation`_ )
- Minimal rdma-core version: v15+ commit 0c5f5765213a ("Merge pull request #227 from yishaih/tm")
(see `RDMA Core installation documentation`_ )
2018-07-12 12:01:31 +00:00
- When building for i686 use:
- rdma-core version 18.0 or above built with 32bit support.
- Kernel version 4.14.41 or above.
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2019-01-09 14:23:19 +00:00
- Starting with rdma-core v21, static libraries can be built::
cd build
CFLAGS=-fPIC cmake -DIN_PLACE=1 -DENABLE_STATIC=1 -GNinja ..
ninja
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.. _`Linux installation documentation`: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/plain/Documentation/admin-guide/README.rst
.. _`RDMA Core installation documentation`: https://raw.githubusercontent.com/linux-rdma/rdma-core/master/README.md
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Mellanox OFED/EN
^^^^^^^^^^^^^^^^
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2020-03-24 11:31:25 +00:00
- Mellanox OFED version: **4.5** and above /
Mellanox EN version: **4.5** and above
2016-11-02 13:46:43 +00:00
- firmware version:
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2017-10-30 10:58:25 +00:00
- ConnectX-4: **12.21.1000** and above.
- ConnectX-4 Lx: **14.21.1000** and above.
- ConnectX-5: **16.21.1000** and above.
- ConnectX-5 Ex: **16.21.1000** and above.
2020-03-24 11:31:25 +00:00
- ConnectX-6: **20.27.0090** and above.
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- ConnectX-6 Dx: **22.27.0090** and above.
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- BlueField: **18.25.1010** and above.
2016-03-03 14:26:43 +00:00
2015-10-30 18:52:42 +00:00
While these libraries and kernel modules are available on OpenFabrics
Alliance's `website <https://www.openfabrics.org/> `__ and provided by package
managers on most distributions, this PMD requires Ethernet extensions that
may not be supported at the moment (this is a work in progress).
`Mellanox OFED
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<http://www.mellanox.com/page/products_dyn?product_family=26&mtag=linux> `__ and
`Mellanox EN
<http://www.mellanox.com/page/products_dyn?product_family=27&mtag=linux> `__
include the necessary support and should be used in the meantime. For DPDK,
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only libibverbs, libmlx5, mlnx-ofed-kernel packages and firmware updates are
required from that distribution.
.. note ::
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Several versions of Mellanox OFED/EN are available. Installing the version
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this DPDK release was developed and tested against is strongly
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recommended. Please check the `linux prerequisites`_ .
Windows Prerequisites
---------------------
This driver relies on external libraries and kernel drivers for resources
allocations and initialization. The dependencies in the following sub-sections
are not part of DPDK, and must be installed separately.
Compilation Prerequisites
~~~~~~~~~~~~~~~~~~~~~~~~~
DevX SDK installation
^^^^^^^^^^^^^^^^^^^^^
The DevX SDK must be installed on the machine building the Windows PMD.
Additional information can be found at
`How to Integrate Windows DevX in Your Development Environment
<https://docs.mellanox.com/display/winof2v250/RShim+Drivers+and+Usage#RShimDriversandUsage-DevXInterface> `__.
Runtime Prerequisites
~~~~~~~~~~~~~~~~~~~~~
WinOF2 version 2.60 or higher must be installed on the machine.
WinOF2 installation
^^^^^^^^^^^^^^^^^^^
The driver can be downloaded from the following site:
`WINOF2
<https://www.mellanox.com/products/adapter-software/ethernet/windows/winof-2> `__
DevX Enablement
^^^^^^^^^^^^^^^
DevX for Windows must be enabled in the Windows registry.
The keys `` DevxEnabled `` and `` DevxFsRules `` must be set.
Additional information can be found in the WinOF2 user manual.
2015-10-30 18:52:42 +00:00
2017-02-09 08:32:01 +00:00
Supported NICs
--------------
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The following Mellanox device families are supported by the same mlx5 driver:
- ConnectX-4
- ConnectX-4 Lx
- ConnectX-5
- ConnectX-5 Ex
- ConnectX-6
- ConnectX-6 Dx
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- ConnectX-6 Lx
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- BlueField
2020-11-24 10:30:35 +00:00
- BlueField-2
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Below are detailed device names:
* Mellanox\ |reg| ConnectX\ |reg|-4 10G MCX4111A-XCAT (1x10G)
* Mellanox\ |reg| ConnectX\ |reg|-4 10G MCX412A-XCAT (2x10G)
* Mellanox\ |reg| ConnectX\ |reg|-4 25G MCX4111A-ACAT (1x25G)
* Mellanox\ |reg| ConnectX\ |reg|-4 25G MCX412A-ACAT (2x25G)
* Mellanox\ |reg| ConnectX\ |reg|-4 40G MCX413A-BCAT (1x40G)
* Mellanox\ |reg| ConnectX\ |reg|-4 40G MCX4131A-BCAT (1x40G)
* Mellanox\ |reg| ConnectX\ |reg|-4 40G MCX415A-BCAT (1x40G)
* Mellanox\ |reg| ConnectX\ |reg|-4 50G MCX413A-GCAT (1x50G)
* Mellanox\ |reg| ConnectX\ |reg|-4 50G MCX4131A-GCAT (1x50G)
* Mellanox\ |reg| ConnectX\ |reg|-4 50G MCX414A-BCAT (2x50G)
* Mellanox\ |reg| ConnectX\ |reg|-4 50G MCX415A-GCAT (1x50G)
* Mellanox\ |reg| ConnectX\ |reg|-4 50G MCX416A-BCAT (2x50G)
* Mellanox\ |reg| ConnectX\ |reg|-4 50G MCX416A-GCAT (2x50G)
* Mellanox\ |reg| ConnectX\ |reg|-4 50G MCX415A-CCAT (1x100G)
* Mellanox\ |reg| ConnectX\ |reg|-4 100G MCX416A-CCAT (2x100G)
* Mellanox\ |reg| ConnectX\ |reg|-4 Lx 10G MCX4111A-XCAT (1x10G)
* Mellanox\ |reg| ConnectX\ |reg|-4 Lx 10G MCX4121A-XCAT (2x10G)
* Mellanox\ |reg| ConnectX\ |reg|-4 Lx 25G MCX4111A-ACAT (1x25G)
* Mellanox\ |reg| ConnectX\ |reg|-4 Lx 25G MCX4121A-ACAT (2x25G)
* Mellanox\ |reg| ConnectX\ |reg|-4 Lx 40G MCX4131A-BCAT (1x40G)
* Mellanox\ |reg| ConnectX\ |reg|-5 100G MCX556A-ECAT (2x100G)
* Mellanox\ |reg| ConnectX\ |reg|-5 Ex EN 100G MCX516A-CDAT (2x100G)
* Mellanox\ |reg| ConnectX\ |reg|-6 200G MCX654106A-HCAT (2x200G)
* Mellanox\ |reg| ConnectX\ |reg|-6 Dx EN 100G MCX623106AN-CDAT (2x100G)
* Mellanox\ |reg| ConnectX\ |reg|-6 Dx EN 200G MCX623105AN-VDAT (1x200G)
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* Mellanox\ |reg| ConnectX\ |reg|-6 Lx EN 25G MCX631102AN-ADAT (2x25G)
2017-02-09 08:32:01 +00:00
2019-01-30 07:53:20 +00:00
Quick Start Guide on OFED/EN
----------------------------
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2021-01-03 10:28:27 +00:00
1. Download latest Mellanox OFED/EN. For more info check the `linux prerequisites`_ .
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2017-07-28 14:28:33 +00:00
2. Install the required libraries and kernel modules either by installing
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only the required set, or by installing the entire Mellanox OFED/EN::
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./mlnxofedinstall --upstream-libs --dpdk
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2019-08-05 15:32:20 +00:00
3. Verify the firmware is the correct one::
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2017-07-28 14:28:33 +00:00
ibv_devinfo
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4. Verify all ports links are set to Ethernet::
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mlxconfig -d <mst device> query | grep LINK_TYPE
LINK_TYPE_P1 ETH(2)
LINK_TYPE_P2 ETH(2)
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Link types may have to be configured to Ethernet::
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mlxconfig -d <mst device> set LINK_TYPE_P1/2=1/2/3
* LINK_TYPE_P1=<1|2|3> , 1=Infiniband 2=Ethernet 3=VPI(auto-sense)
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For hypervisors, verify SR-IOV is enabled on the NIC::
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mlxconfig -d <mst device> query | grep SRIOV_EN
SRIOV_EN True(1)
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If needed, configure SR-IOV::
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mlxconfig -d <mst device> set SRIOV_EN=1 NUM_OF_VFS=16
mlxfwreset -d <mst device> reset
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5. Restart the driver::
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/etc/init.d/openibd restart
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or::
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service openibd restart
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If link type was changed, firmware must be reset as well::
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mlxfwreset -d <mst device> reset
For hypervisors, after reset write the sysfs number of virtual functions
needed for the PF.
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To dynamically instantiate a given number of virtual functions (VFs)::
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echo [num_vfs] > /sys/class/infiniband/mlx5_0/device/sriov_numvfs
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6. Install DPDK and you are ready to go.
See :doc: `compilation instructions <../linux_gsg/build_dpdk>` .
2017-07-28 14:28:33 +00:00
2019-05-13 11:41:02 +00:00
Enable switchdev mode
---------------------
Switchdev mode is a mode in E-Switch, that binds between representor and VF.
Representor is a port in DPDK that is connected to a VF in such a way
that assuming there are no offload flows, each packet that is sent from the VF
will be received by the corresponding representor. While each packet that is
sent to a representor will be received by the VF.
This is very useful in case of SRIOV mode, where the first packet that is sent
by the VF will be received by the DPDK application which will decide if this
flow should be offloaded to the E-Switch. After offloading the flow packet
that the VF that are matching the flow will not be received any more by
the DPDK application.
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1. Enable SRIOV mode::
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mlxconfig -d <mst device> set SRIOV_EN=true
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2. Configure the max number of VFs::
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mlxconfig -d <mst device> set NUM_OF_VFS=<num of vfs>
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3. Reset the FW::
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mlxfwreset -d <mst device> reset
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3. Configure the actual number of VFs::
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echo <num of vfs > /sys/class/net/<net device>/device/sriov_numvfs
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4. Unbind the device (can be rebind after the switchdev mode)::
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echo -n "<device pci address" > /sys/bus/pci/drivers/mlx5_core/unbind
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5. Enbale switchdev mode::
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echo switchdev > /sys/class/net/<net device>/compat/devlink/mode
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Performance tuning
------------------
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1. Configure aggressive CQE Zipping for maximum performance::
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mlxconfig -d <mst device> s CQE_COMPRESSION=1
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To set it back to the default CQE Zipping mode use::
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mlxconfig -d <mst device> s CQE_COMPRESSION=0
2. In case of virtualization:
- Make sure that hypervisor kernel is 3.16 or newer.
- Configure boot with `` iommu=pt `` .
- Use 1G huge pages.
- Make sure to allocate a VM on huge pages.
- Make sure to set CPU pinning.
3. Use the CPU near local NUMA node to which the PCIe adapter is connected,
for better performance. For VMs, verify that the right CPU
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and NUMA node are pinned according to the above. Run::
2017-07-28 14:28:33 +00:00
lstopo-no-graphics
to identify the NUMA node to which the PCIe adapter is connected.
4. If more than one adapter is used, and root complex capabilities allow
to put both adapters on the same NUMA node without PCI bandwidth degradation,
it is recommended to locate both adapters on the same NUMA node.
This in order to forward packets from one to the other without
NUMA performance penalty.
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5. Disable pause frames::
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ethtool -A <netdev> rx off tx off
6. Verify IO non-posted prefetch is disabled by default. This can be checked
via the BIOS configuration. Please contact you server provider for more
information about the settings.
.. note ::
On some machines, depends on the machine integrator, it is beneficial
to set the PCI max read request parameter to 1K. This can be
done in the following way:
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To query the read request size use::
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setpci -s <NIC PCI address> 68.w
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If the output is different than 3XXX, set it by::
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setpci -s <NIC PCI address> 68.w=3XXX
The XXX can be different on different systems. Make sure to configure
according to the setpci output.
2017-06-13 10:20:58 +00:00
net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
7. To minimize overhead of searching Memory Regions:
- '--socket-mem' is recommended to pin memory by predictable amount.
- Configure per-lcore cache when creating Mempools for packet buffer.
- Refrain from dynamically allocating/freeing memory in run-time.
2020-11-24 07:44:16 +00:00
Rx burst functions
------------------
There are multiple Rx burst functions with different advantages and limitations.
.. table :: Rx burst functions
+-------------------+------------------------+---------+-----------------+------+-------+
|| Function Name || Enabler || Scatter|| Error Recovery || CQE || Large|
| | | | || comp|| MTU |
+===================+========================+=========+=================+======+=======+
| rx_burst | rx_vec_en=0 | Yes | Yes | Yes | Yes |
+-------------------+------------------------+---------+-----------------+------+-------+
| rx_burst_vec | rx_vec_en=1 (default) | No | if CQE comp off | Yes | No |
+-------------------+------------------------+---------+-----------------+------+-------+
| rx_burst_mprq || mprq_en=1 | No | Yes | Yes | Yes |
| || RxQs >= rxqs_min_mprq | | | | |
+-------------------+------------------------+---------+-----------------+------+-------+
| rx_burst_mprq_vec || rx_vec_en=1 (default) | No | if CQE comp off | Yes | Yes |
| || mprq_en=1 | | | | |
| || RxQs >= rxqs_min_mprq | | | | |
+-------------------+------------------------+---------+-----------------+------+-------+
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.. _mlx5_offloads_support:
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Supported hardware offloads
---------------------------
.. table :: Minimal SW/HW versions for queue offloads
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============== ===== ===== ========= ===== ========== =============
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Offload DPDK Linux rdma-core OFED firmware hardware
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============== ===== ===== ========= ===== ========== =============
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common base 17.11 4.14 16 4.2-1 12.21.1000 ConnectX-4
checksums 17.11 4.14 16 4.2-1 12.21.1000 ConnectX-4
Rx timestamp 17.11 4.14 16 4.2-1 12.21.1000 ConnectX-4
TSO 17.11 4.14 16 4.2-1 12.21.1000 ConnectX-4
LRO 19.08 N/A N/A 4.6-4 16.25.6406 ConnectX-5
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Buffer Split 20.11 N/A N/A 5.1-2 22.28.2006 ConnectX-6 Dx
============== ===== ===== ========= ===== ========== =============
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.. table :: Minimal SW/HW versions for rte_flow offloads
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+-----------------------+-----------------+-----------------+
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| Offload | with E-Switch | with NIC |
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+=======================+=================+=================+
| Count | | DPDK 19.05 | | DPDK 19.02 |
| | | OFED 4.6 | | OFED 4.6 |
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| | | rdma-core 24 | | rdma-core 23 |
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| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| Drop | | DPDK 19.05 | | DPDK 18.11 |
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| | | OFED 4.6 | | OFED 4.5 |
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| | | rdma-core 24 | | rdma-core 23 |
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| | | ConnectX-5 | | ConnectX-4 |
+-----------------------+-----------------+-----------------+
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| Queue / RSS | | | | DPDK 18.11 |
| | | N/A | | OFED 4.5 |
| | | | | rdma-core 23 |
| | | | | ConnectX-4 |
+-----------------------+-----------------+-----------------+
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| RSS shared action | | | | DPDK 20.11 |
| | | N/A | | OFED 5.2 |
| | | | | rdma-core 33 |
| | | | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
| | VLAN | | DPDK 19.11 | | DPDK 19.11 |
| | (of_pop_vlan / | | OFED 4.7-1 | | OFED 4.7-1 |
| | of_push_vlan / | | ConnectX-5 | | ConnectX-5 |
| | of_set_vlan_pcp / | | | | |
| | of_set_vlan_vid) | | | | |
+-----------------------+-----------------+-----------------+
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| Encapsulation | | DPDK 19.05 | | DPDK 19.02 |
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| (VXLAN / NVGRE / RAW) | | OFED 4.7-1 | | OFED 4.6 |
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| | | rdma-core 24 | | rdma-core 23 |
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| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| Encapsulation | | DPDK 19.11 | | DPDK 19.11 |
| GENEVE | | OFED 4.7-3 | | OFED 4.7-3 |
| | | rdma-core 27 | | rdma-core 27 |
| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| Tunnel Offload | | DPDK 20.11 | | DPDK 20.11 |
| | | OFED 5.1-2 | | OFED 5.1-2 |
| | | rdma-core 32 | | N/A |
| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| | Header rewrite | | DPDK 19.05 | | DPDK 19.02 |
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| | (set_ipv4_src / | | OFED 4.7-1 | | OFED 4.7-1 |
| | set_ipv4_dst / | | rdma-core 24 | | rdma-core 24 |
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| | set_ipv6_src / | | ConnectX-5 | | ConnectX-5 |
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| | set_ipv6_dst / | | | | |
| | set_tp_src / | | | | |
| | set_tp_dst / | | | | |
| | dec_ttl / | | | | |
| | set_ttl / | | | | |
| | set_mac_src / | | | | |
| | set_mac_dst) | | | | |
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+-----------------------+-----------------+-----------------+
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| | Header rewrite | | DPDK 20.02 | | DPDK 20.02 |
| | (set_dscp) | | OFED 5.0 | | OFED 5.0 |
| | | | rdma-core 24 | | rdma-core 24 |
| | | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| Jump | | DPDK 19.05 | | DPDK 19.02 |
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| | | OFED 4.7-1 | | OFED 4.7-1 |
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| | | rdma-core 24 | | N/A |
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| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
| Mark / Flag | | DPDK 19.05 | | DPDK 18.11 |
| | | OFED 4.6 | | OFED 4.5 |
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| | | rdma-core 24 | | rdma-core 23 |
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| | | ConnectX-5 | | ConnectX-4 |
+-----------------------+-----------------+-----------------+
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| Meta data | | DPDK 19.11 | | DPDK 19.11 |
| | | OFED 4.7-3 | | OFED 4.7-3 |
| | | rdma-core 26 | | rdma-core 26 |
| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| Port ID | | DPDK 19.05 | | N/A |
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| | | OFED 4.7-1 | | N/A |
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| | | rdma-core 24 | | N/A |
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| | | ConnectX-5 | | N/A |
+-----------------------+-----------------+-----------------+
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| Hairpin | | | | DPDK 19.11 |
| | | N/A | | OFED 4.7-3 |
| | | | | rdma-core 26 |
| | | | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| 2-port Hairpin | | | | DPDK 20.11 |
| | | N/A | | OFED 5.1-2 |
| | | | | N/A |
| | | | | ConnectX-5 |
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+-----------------------+-----------------+-----------------+
| Metering | | DPDK 19.11 | | DPDK 19.11 |
| | | OFED 4.7-3 | | OFED 4.7-3 |
| | | rdma-core 26 | | rdma-core 26 |
| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
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| Sampling | | DPDK 20.11 | | DPDK 20.11 |
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| | | OFED 5.1-2 | | OFED 5.1-2 |
| | | rdma-core 32 | | N/A |
| | | ConnectX-5 | | ConnectX-5 |
+-----------------------+-----------------+-----------------+
| Age shared action | | DPDK 20.11 | | DPDK 20.11 |
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| | | OFED 5.2 | | OFED 5.2 |
| | | rdma-core 32 | | rdma-core 32 |
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| | | ConnectX-6 Dx| | ConnectX-6 Dx |
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+-----------------------+-----------------+-----------------+
2021-01-11 18:21:52 +00:00
| Encapsulation | | DPDK 21.02 | | DPDK 21.02 |
| GTP PSC | | OFED 5.2 | | OFED 5.2 |
| | | rdma-core 35 | | rdma-core 35 |
| | | ConnectX-6 Dx| | ConnectX-6 Dx |
+-----------------------+-----------------+-----------------+
2021-01-17 10:21:22 +00:00
| Encapsulation | | DPDK 21.02 | | DPDK 21.02 |
| GENEVE TLV option | | OFED 5.2 | | OFED 5.2 |
| | | rdma-core 34 | | rdma-core 34 |
| | | ConnectX-6 Dx | | ConnectX-6 Dx |
+-----------------------+-----------------+-----------------+
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2020-03-26 10:22:00 +00:00
Notes for metadata
------------------
MARK and META items are interrelated with datapath - they might move from/to
the applications in mbuf fields. Hence, zero value for these items has the
special meaning - it means "no metadata are provided", not zero values are
treated by applications and PMD as valid ones.
Moreover in the flow engine domain the value zero is acceptable to match and
set, and we should allow to specify zero values as rte_flow parameters for the
META and MARK items and actions. In the same time zero mask has no meaning and
should be rejected on validation stage.
2020-04-22 15:27:15 +00:00
Notes for rte_flow
------------------
Flows are not cached in the driver.
When stopping a device port, all the flows created on this port from the
application will be flushed automatically in the background.
After stopping the device port, all flows on this port become invalid and
not represented in the system.
All references to these flows held by the application should be discarded
directly but neither destroyed nor flushed.
The application should re-create the flows as required after the port restart.
2015-12-12 19:43:24 +00:00
Notes for testpmd
-----------------
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Compared to librte_net_mlx4 that implements a single RSS configuration per
port, librte_net_mlx5 supports per-protocol RSS configuration.
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Since `` testpmd `` defaults to IP RSS mode and there is currently no
command-line parameter to enable additional protocols (UDP and TCP as well
as IP), the following commands must be entered from its CLI to get the same
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behavior as librte_net_mlx4::
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> port stop all
> port config all rss all
> port start all
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Usage example
-------------
2017-01-06 00:49:31 +00:00
This section demonstrates how to launch **testpmd** with Mellanox
2020-11-03 12:36:02 +00:00
ConnectX-4/ConnectX-5/ConnectX-6/BlueField devices managed by librte_net_mlx5.
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2019-08-05 15:32:20 +00:00
#. Load the kernel modules::
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modprobe -a ib_uverbs mlx5_core mlx5_ib
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Alternatively if MLNX_OFED/MLNX_EN is fully installed, the following script
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can be run::
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/etc/init.d/openibd restart
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.. note ::
User space I/O kernel modules (uio and igb_uio) are not used and do
not have to be loaded.
#. Make sure Ethernet interfaces are in working order and linked to kernel
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verbs. Related sysfs entries should be present::
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ls -d /sys/class/net/*/device/infiniband_verbs/uverbs* | cut -d / -f 5
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Example output::
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eth30
eth31
eth32
eth33
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#. Optionally, retrieve their PCI bus addresses for to be used with the allow list::
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{
for intf in eth2 eth3 eth4 eth5;
do
(cd "/sys/class/net/${intf}/device/" && pwd -P);
done;
} |
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sed -n 's,.*/\(.* \),-a \1,p'
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Example output::
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-a 0000:05:00.1
-a 0000:06:00.0
-a 0000:06:00.1
-a 0000:05:00.0
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#. Request huge pages::
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echo 1024 > /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages/nr_hugepages
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#. Start testpmd with basic parameters::
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testpmd -l 8-15 -n 4 -a 05:00.0 -a 05:00.1 -a 06:00.0 -a 06:00.1 -- --rxq=2 --txq=2 -i
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Example output::
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[...]
EAL: PCI device 0000:05:00.0 on NUMA socket 0
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EAL: probe driver: 15b3:1013 librte_net_mlx5
PMD: librte_net_mlx5: PCI information matches, using device "mlx5_0" (VF: false)
PMD: librte_net_mlx5: 1 port(s) detected
PMD: librte_net_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fe
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EAL: PCI device 0000:05:00.1 on NUMA socket 0
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EAL: probe driver: 15b3:1013 librte_net_mlx5
PMD: librte_net_mlx5: PCI information matches, using device "mlx5_1" (VF: false)
PMD: librte_net_mlx5: 1 port(s) detected
PMD: librte_net_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:ff
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EAL: PCI device 0000:06:00.0 on NUMA socket 0
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EAL: probe driver: 15b3:1013 librte_net_mlx5
PMD: librte_net_mlx5: PCI information matches, using device "mlx5_2" (VF: false)
PMD: librte_net_mlx5: 1 port(s) detected
PMD: librte_net_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fa
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EAL: PCI device 0000:06:00.1 on NUMA socket 0
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EAL: probe driver: 15b3:1013 librte_net_mlx5
PMD: librte_net_mlx5: PCI information matches, using device "mlx5_3" (VF: false)
PMD: librte_net_mlx5: 1 port(s) detected
PMD: librte_net_mlx5: port 1 MAC address is e4:1d:2d:e7:0c:fb
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Interactive-mode selected
Configuring Port 0 (socket 0)
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PMD: librte_net_mlx5: 0x8cba80: TX queues number update: 0 -> 2
PMD: librte_net_mlx5: 0x8cba80: RX queues number update: 0 -> 2
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Port 0: E4:1D:2D:E7:0C:FE
Configuring Port 1 (socket 0)
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PMD: librte_net_mlx5: 0x8ccac8: TX queues number update: 0 -> 2
PMD: librte_net_mlx5: 0x8ccac8: RX queues number update: 0 -> 2
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Port 1: E4:1D:2D:E7:0C:FF
Configuring Port 2 (socket 0)
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PMD: librte_net_mlx5: 0x8cdb10: TX queues number update: 0 -> 2
PMD: librte_net_mlx5: 0x8cdb10: RX queues number update: 0 -> 2
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Port 2: E4:1D:2D:E7:0C:FA
Configuring Port 3 (socket 0)
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PMD: librte_net_mlx5: 0x8ceb58: TX queues number update: 0 -> 2
PMD: librte_net_mlx5: 0x8ceb58: RX queues number update: 0 -> 2
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Port 3: E4:1D:2D:E7:0C:FB
Checking link statuses...
Port 0 Link Up - speed 40000 Mbps - full-duplex
Port 1 Link Up - speed 40000 Mbps - full-duplex
Port 2 Link Up - speed 10000 Mbps - full-duplex
Port 3 Link Up - speed 10000 Mbps - full-duplex
Done
testpmd>
2020-01-17 11:56:03 +00:00
How to dump flows
-----------------
This section demonstrates how to dump flows. Currently, it's possible to dump
all flows with assistance of external tools.
#. 2 ways to get flow raw file:
- Using testpmd CLI:
.. code-block :: console
testpmd> flow dump <port> <output_file>
- call rte_flow_dev_dump api:
.. code-block :: console
rte_flow_dev_dump(port, file, NULL);
#. Dump human-readable flows from raw file:
Get flow parsing tool from: https://github.com/Mellanox/mlx_steering_dump
.. code-block :: console
mlx_steering_dump.py -f <output_file>
