193 lines
7.5 KiB
C
193 lines
7.5 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
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* Copyright(c) 2018 Synopsys, Inc. All rights reserved.
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*/
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#ifndef __AXGBE_PHY_H__
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#define __AXGBE_PHY_H__
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#define SPEED_10 10
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#define SPEED_100 100
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#define SPEED_1000 1000
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#define SPEED_2500 2500
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#define SPEED_10000 10000
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/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit
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* IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips.
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*/
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#define MII_ADDR_C45 (1 << 30)
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/* Basic mode status register. */
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#define BMSR_LSTATUS 0x0004 /* Link status */
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/* Status register 1. */
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#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
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/* Generic MII registers. */
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#define MII_BMCR 0x00 /* Basic mode control register */
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#define MII_BMSR 0x01 /* Basic mode status register */
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#define MII_PHYSID1 0x02 /* PHYS ID 1 */
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#define MII_PHYSID2 0x03 /* PHYS ID 2 */
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#define MII_ADVERTISE 0x04 /* Advertisement control reg */
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#define MII_LPA 0x05 /* Link partner ability reg */
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#define MII_EXPANSION 0x06 /* Expansion register */
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#define MII_CTRL1000 0x09 /* 1000BASE-T control */
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#define MII_STAT1000 0x0a /* 1000BASE-T status */
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#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
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#define MII_MMD_DATA 0x0e /* MMD Access Data Register */
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#define MII_ESTATUS 0x0f /* Extended Status */
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#define MII_DCOUNTER 0x12 /* Disconnect counter */
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#define MII_FCSCOUNTER 0x13 /* False carrier counter */
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#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_SREVISION 0x16 /* Silicon revision */
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#define MII_RESV1 0x17 /* Reserved... */
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#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
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#define MII_PHYADDR 0x19 /* PHY address */
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#define MII_RESV2 0x1a /* Reserved... */
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#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
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#define MII_NCONFIG 0x1c /* Network interface config */
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/* Basic mode control register. */
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#define BMCR_RESV 0x003f /* Unused... */
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#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
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#define BMCR_CTST 0x0080 /* Collision test */
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#define BMCR_FULLDPLX 0x0100 /* Full duplex */
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#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
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#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
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#define BMCR_PDOWN 0x0800 /* Enable low power state */
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset to default state */
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#define BMCR_SPEED10 0x0000 /* Select 10Mbps */
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/* MDIO Manageable Devices (MMDs). */
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#define MDIO_MMD_PMAPMD 1 /* Physical Medium Attachment
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* Physical Medium Dependent
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*/
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#define MDIO_MMD_WIS 2 /* WAN Interface Sublayer */
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#define MDIO_MMD_PCS 3 /* Physical Coding Sublayer */
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#define MDIO_MMD_PHYXS 4 /* PHY Extender Sublayer */
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#define MDIO_MMD_DTEXS 5 /* DTE Extender Sublayer */
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#define MDIO_MMD_TC 6 /* Transmission Convergence */
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#define MDIO_MMD_AN 7 /* Auto-Negotiation */
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#define MDIO_MMD_C22EXT 29 /* Clause 22 extension */
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#define MDIO_MMD_VEND1 30 /* Vendor specific 1 */
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#define MDIO_MMD_VEND2 31 /* Vendor specific 2 */
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/* Generic MDIO registers. */
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#define MDIO_CTRL1 MII_BMCR
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#define MDIO_STAT1 MII_BMSR
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#define MDIO_DEVID1 MII_PHYSID1
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#define MDIO_DEVID2 MII_PHYSID2
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#define MDIO_SPEED 4 /* Speed ability */
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#define MDIO_DEVS1 5 /* Devices in package */
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#define MDIO_DEVS2 6
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#define MDIO_CTRL2 7 /* 10G control 2 */
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#define MDIO_STAT2 8 /* 10G status 2 */
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#define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
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#define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
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#define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
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#define MDIO_PKGID1 14 /* Package identifier */
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#define MDIO_PKGID2 15
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#define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
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#define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
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#define MDIO_PCS_EEE_ABLE 20 /* EEE Capability register */
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#define MDIO_PCS_EEE_WK_ERR 22 /* EEE wake error counter */
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#define MDIO_PHYXS_LNSTAT 24 /* PHY XGXS lane state */
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#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
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#define MDIO_AN_EEE_LPABLE 61 /* EEE link partner ability */
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/* Media-dependent registers. */
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#define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
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#define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
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#define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
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* Lanes B-D are numbered 134-136.
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*/
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#define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
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#define MDIO_PCS_10GBX_STAT1 24 /* 10GBASE-X PCS status 1 */
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#define MDIO_PCS_10GBRT_STAT1 32 /* 10GBASE-R/-T PCS status 1 */
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#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
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#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
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#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
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/* Control register 1. */
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/* Enable extended speed selection */
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#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
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/* All speed selection bits */
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#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
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#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
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#define MDIO_CTRL1_LPOWER BMCR_PDOWN
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#define MDIO_CTRL1_RESET BMCR_RESET
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#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
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#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
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#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
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#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
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#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
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#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
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#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
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#define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
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#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
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/* PMA 10GBASE-R FEC ability register. */
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#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 /* FEC ability */
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#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 /* FEC error indic. ability */
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/* Autoneg related */
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#define ADVERTISED_Autoneg (1 << 6)
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#define SUPPORTED_Autoneg (1 << 6)
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#define AUTONEG_DISABLE 0x00
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#define AUTONEG_ENABLE 0x01
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#define ADVERTISED_Pause (1 << 13)
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#define ADVERTISED_Asym_Pause (1 << 14)
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#define SUPPORTED_Pause (1 << 13)
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#define SUPPORTED_Asym_Pause (1 << 14)
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#define SUPPORTED_Backplane (1 << 16)
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#define SUPPORTED_TP (1 << 7)
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#define ADVERTISED_10000baseR_FEC (1 << 20)
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#define SUPPORTED_10000baseR_FEC (1 << 20)
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#define SUPPORTED_FIBRE (1 << 10)
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#define ADVERTISED_10000baseKR_Full (1 << 19)
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#define ADVERTISED_10000baseT_Full (1 << 12)
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#define ADVERTISED_2500baseX_Full (1 << 15)
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#define ADVERTISED_1000baseKX_Full (1 << 17)
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#define ADVERTISED_1000baseT_Full (1 << 5)
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#define ADVERTISED_100baseT_Full (1 << 3)
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#define ADVERTISED_TP (1 << 7)
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#define ADVERTISED_FIBRE (1 << 10)
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#define ADVERTISED_Backplane (1 << 16)
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#define SUPPORTED_1000baseKX_Full (1 << 17)
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#define SUPPORTED_10000baseKR_Full (1 << 19)
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#define SUPPORTED_2500baseX_Full (1 << 15)
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#define SUPPORTED_100baseT_Full (1 << 2)
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#define SUPPORTED_1000baseT_Full (1 << 5)
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#define SUPPORTED_10000baseT_Full (1 << 12)
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#define SUPPORTED_2500baseX_Full (1 << 15)
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#define SPEED_UNKNOWN -1
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/* Duplex, half or full. */
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#define DUPLEX_HALF 0x00
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#define DUPLEX_FULL 0x01
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#define DUPLEX_UNKNOWN 0xff
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#endif
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/* PHY */
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