common/cpt: support ZUC and SNOW3G
Adding microcode interface for supporting ZUC and SNOW3G. Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com> Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com> Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com> Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com> Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com> Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com> Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
This commit is contained in:
Srisivasubramanian S
Akhil Goyal
parent
ba48221f4a
commit
00d92c66a1
@ -1226,6 +1226,596 @@ cpt_dec_hmac_prep(uint32_t flags,
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return 0;
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}
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static __rte_always_inline int
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cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
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uint64_t d_offs,
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uint64_t d_lens,
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fc_params_t *params,
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void *op,
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void **prep_req)
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{
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uint32_t size;
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int32_t inputlen, outputlen;
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struct cpt_ctx *cpt_ctx;
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uint32_t mac_len = 0;
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uint8_t snow3g, j;
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struct cpt_request_info *req;
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buf_ptr_t *buf_p;
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uint32_t encr_offset = 0, auth_offset = 0;
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uint32_t encr_data_len = 0, auth_data_len = 0;
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int flags, iv_len = 16, m_size;
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void *m_vaddr, *c_vaddr;
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uint64_t m_dma, c_dma, offset_ctrl;
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uint64_t *offset_vaddr, offset_dma;
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uint32_t *iv_s, iv[4];
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vq_cmd_word0_t vq_cmd_w0;
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vq_cmd_word3_t vq_cmd_w3;
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opcode_info_t opcode;
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buf_p = ¶ms->meta_buf;
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m_vaddr = buf_p->vaddr;
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m_dma = buf_p->dma_addr;
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m_size = buf_p->size;
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cpt_ctx = params->ctx_buf.vaddr;
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flags = cpt_ctx->zsk_flags;
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mac_len = cpt_ctx->mac_len;
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snow3g = cpt_ctx->snow3g;
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/*
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* Save initial space that followed app data for completion code &
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* alternate completion code to fall in same cache line as app data
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*/
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m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
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m_dma += COMPLETION_CODE_SIZE;
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size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
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(uint8_t *)m_vaddr;
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c_vaddr = (uint8_t *)m_vaddr + size;
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c_dma = m_dma + size;
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size += sizeof(cpt_res_s_t);
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m_vaddr = (uint8_t *)m_vaddr + size;
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m_dma += size;
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m_size -= size;
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/* Reserve memory for cpt request info */
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req = m_vaddr;
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size = sizeof(struct cpt_request_info);
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m_vaddr = (uint8_t *)m_vaddr + size;
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m_dma += size;
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m_size -= size;
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opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
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/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
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opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
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(0 << 3) | (flags & 0x7));
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if (flags == 0x1) {
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/*
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* Microcode expects offsets in bytes
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* TODO: Rounding off
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*/
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auth_data_len = AUTH_DLEN(d_lens);
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/* EIA3 or UIA2 */
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auth_offset = AUTH_OFFSET(d_offs);
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auth_offset = auth_offset / 8;
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/* consider iv len */
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auth_offset += iv_len;
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inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
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outputlen = mac_len;
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offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
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} else {
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/* EEA3 or UEA2 */
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/*
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* Microcode expects offsets in bytes
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* TODO: Rounding off
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*/
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encr_data_len = ENCR_DLEN(d_lens);
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encr_offset = ENCR_OFFSET(d_offs);
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encr_offset = encr_offset / 8;
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/* consider iv len */
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encr_offset += iv_len;
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inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
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outputlen = inputlen;
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/* iv offset is 0 */
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offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
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}
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/* IV */
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iv_s = (flags == 0x1) ? params->auth_iv_buf :
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params->iv_buf;
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if (snow3g) {
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/*
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* DPDK seems to provide it in form of IV3 IV2 IV1 IV0
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* and BigEndian, MC needs it as IV0 IV1 IV2 IV3
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*/
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for (j = 0; j < 4; j++)
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iv[j] = iv_s[3 - j];
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} else {
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/* ZUC doesn't need a swap */
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for (j = 0; j < 4; j++)
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iv[j] = iv_s[j];
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}
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/*
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* GP op header, lengths are expected in bits.
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*/
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vq_cmd_w0.u64 = 0;
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vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
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vq_cmd_w0.s.param2 = rte_cpu_to_be_16(auth_data_len);
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/*
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* In 83XX since we have a limitation of
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* IV & Offset control word not part of instruction
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* and need to be part of Data Buffer, we check if
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* head room is there and then only do the Direct mode processing
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*/
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if (likely((req_flags & SINGLE_BUF_INPLACE) &&
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(req_flags & SINGLE_BUF_HEADTAILROOM))) {
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void *dm_vaddr = params->bufs[0].vaddr;
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uint64_t dm_dma_addr = params->bufs[0].dma_addr;
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/*
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* This flag indicates that there is 24 bytes head room and
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* 8 bytes tail room available, so that we get to do
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* DIRECT MODE with limitation
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*/
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offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
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OFF_CTRL_LEN - iv_len);
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offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
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/* DPTR */
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req->ist.ei1 = offset_dma;
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/* RPTR should just exclude offset control word */
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req->ist.ei2 = dm_dma_addr - iv_len;
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req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
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+ outputlen - iv_len);
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vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
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vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
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if (likely(iv_len)) {
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uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
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+ OFF_CTRL_LEN);
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memcpy(iv_d, iv, 16);
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}
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*offset_vaddr = offset_ctrl;
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} else {
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uint32_t i, g_size_bytes, s_size_bytes;
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uint64_t dptr_dma, rptr_dma;
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sg_comp_t *gather_comp;
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sg_comp_t *scatter_comp;
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uint8_t *in_buffer;
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uint32_t *iv_d;
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/* save space for iv */
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offset_vaddr = m_vaddr;
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offset_dma = m_dma;
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m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
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m_dma += OFF_CTRL_LEN + iv_len;
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m_size -= OFF_CTRL_LEN + iv_len;
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opcode.s.major |= CPT_DMA_MODE;
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vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
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/* DPTR has SG list */
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in_buffer = m_vaddr;
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dptr_dma = m_dma;
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((uint16_t *)in_buffer)[0] = 0;
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((uint16_t *)in_buffer)[1] = 0;
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/* TODO Add error check if space will be sufficient */
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gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
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/*
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* Input Gather List
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*/
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i = 0;
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/* Offset control word followed by iv */
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i = fill_sg_comp(gather_comp, i, offset_dma,
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OFF_CTRL_LEN + iv_len);
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/* iv offset is 0 */
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*offset_vaddr = offset_ctrl;
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iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
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memcpy(iv_d, iv, 16);
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/* input data */
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size = inputlen - iv_len;
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if (size) {
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i = fill_sg_comp_from_iov(gather_comp, i,
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params->src_iov,
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0, &size, NULL, 0);
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if (size)
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return ERR_BAD_INPUT_ARG;
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}
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((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
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g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
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/*
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* Output Scatter List
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*/
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i = 0;
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scatter_comp =
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(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
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if (flags == 0x1) {
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/* IV in SLIST only for EEA3 & UEA2 */
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iv_len = 0;
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}
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if (iv_len) {
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i = fill_sg_comp(scatter_comp, i,
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offset_dma + OFF_CTRL_LEN, iv_len);
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}
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/* Add output data */
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if (req_flags & VALID_MAC_BUF) {
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size = outputlen - iv_len - mac_len;
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if (size) {
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i = fill_sg_comp_from_iov(scatter_comp, i,
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params->dst_iov, 0,
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&size, NULL, 0);
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if (size)
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return ERR_BAD_INPUT_ARG;
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}
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/* mac data */
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if (mac_len) {
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i = fill_sg_comp_from_buf(scatter_comp, i,
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¶ms->mac_buf);
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}
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} else {
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/* Output including mac */
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size = outputlen - iv_len;
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if (size) {
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i = fill_sg_comp_from_iov(scatter_comp, i,
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params->dst_iov, 0,
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&size, NULL, 0);
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if (size)
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return ERR_BAD_INPUT_ARG;
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}
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}
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((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
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s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
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size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
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/* This is DPTR len incase of SG mode */
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vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
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m_vaddr = (uint8_t *)m_vaddr + size;
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m_dma += size;
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m_size -= size;
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/* cpt alternate completion address saved earlier */
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req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
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*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
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rptr_dma = c_dma - 8;
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req->ist.ei1 = dptr_dma;
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req->ist.ei2 = rptr_dma;
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}
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/* First 16-bit swap then 64-bit swap */
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/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
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* to eliminate all the swapping
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*/
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vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
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/* vq command w3 */
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vq_cmd_w3.u64 = 0;
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vq_cmd_w3.s.grp = 0;
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vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
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offsetof(struct cpt_ctx, zs_ctx);
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/* 16 byte aligned cpt res address */
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req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
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*req->completion_addr = COMPLETION_CODE_INIT;
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req->comp_baddr = c_dma;
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/* Fill microcode part of instruction */
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req->ist.ei0 = vq_cmd_w0.u64;
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req->ist.ei3 = vq_cmd_w3.u64;
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req->op = op;
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*prep_req = req;
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return 0;
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}
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static __rte_always_inline int
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cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
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uint64_t d_offs,
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uint64_t d_lens,
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fc_params_t *params,
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void *op,
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void **prep_req)
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{
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uint32_t size;
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int32_t inputlen = 0, outputlen;
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struct cpt_ctx *cpt_ctx;
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uint8_t snow3g, iv_len = 16;
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struct cpt_request_info *req;
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buf_ptr_t *buf_p;
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uint32_t encr_offset;
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uint32_t encr_data_len;
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int flags, m_size;
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void *m_vaddr, *c_vaddr;
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uint64_t m_dma, c_dma;
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uint64_t *offset_vaddr, offset_dma;
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uint32_t *iv_s, iv[4], j;
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vq_cmd_word0_t vq_cmd_w0;
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vq_cmd_word3_t vq_cmd_w3;
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opcode_info_t opcode;
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buf_p = ¶ms->meta_buf;
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m_vaddr = buf_p->vaddr;
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m_dma = buf_p->dma_addr;
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m_size = buf_p->size;
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/*
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* Microcode expects offsets in bytes
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* TODO: Rounding off
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*/
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encr_offset = ENCR_OFFSET(d_offs) / 8;
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encr_data_len = ENCR_DLEN(d_lens);
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cpt_ctx = params->ctx_buf.vaddr;
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flags = cpt_ctx->zsk_flags;
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snow3g = cpt_ctx->snow3g;
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/*
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* Save initial space that followed app data for completion code &
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* alternate completion code to fall in same cache line as app data
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*/
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m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
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m_dma += COMPLETION_CODE_SIZE;
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size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
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(uint8_t *)m_vaddr;
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c_vaddr = (uint8_t *)m_vaddr + size;
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c_dma = m_dma + size;
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size += sizeof(cpt_res_s_t);
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m_vaddr = (uint8_t *)m_vaddr + size;
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m_dma += size;
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m_size -= size;
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/* Reserve memory for cpt request info */
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req = m_vaddr;
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size = sizeof(struct cpt_request_info);
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m_vaddr = (uint8_t *)m_vaddr + size;
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m_dma += size;
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m_size -= size;
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opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
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/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
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opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
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(0 << 3) | (flags & 0x7));
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/* consider iv len */
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encr_offset += iv_len;
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inputlen = encr_offset +
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(RTE_ALIGN(encr_data_len, 8) / 8);
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outputlen = inputlen;
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/* IV */
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iv_s = params->iv_buf;
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if (snow3g) {
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/*
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* DPDK seems to provide it in form of IV3 IV2 IV1 IV0
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* and BigEndian, MC needs it as IV0 IV1 IV2 IV3
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*/
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for (j = 0; j < 4; j++)
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iv[j] = iv_s[3 - j];
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} else {
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/* ZUC doesn't need a swap */
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for (j = 0; j < 4; j++)
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iv[j] = iv_s[j];
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}
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/*
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* GP op header, lengths are expected in bits.
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*/
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vq_cmd_w0.u64 = 0;
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vq_cmd_w0.s.param1 = rte_cpu_to_be_16(encr_data_len);
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/*
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* In 83XX since we have a limitation of
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* IV & Offset control word not part of instruction
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* and need to be part of Data Buffer, we check if
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* head room is there and then only do the Direct mode processing
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*/
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if (likely((req_flags & SINGLE_BUF_INPLACE) &&
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(req_flags & SINGLE_BUF_HEADTAILROOM))) {
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void *dm_vaddr = params->bufs[0].vaddr;
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uint64_t dm_dma_addr = params->bufs[0].dma_addr;
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/*
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* This flag indicates that there is 24 bytes head room and
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* 8 bytes tail room available, so that we get to do
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* DIRECT MODE with limitation
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*/
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offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
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OFF_CTRL_LEN - iv_len);
|
||||
offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
|
||||
|
||||
/* DPTR */
|
||||
req->ist.ei1 = offset_dma;
|
||||
/* RPTR should just exclude offset control word */
|
||||
req->ist.ei2 = dm_dma_addr - iv_len;
|
||||
req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
|
||||
+ outputlen - iv_len);
|
||||
|
||||
vq_cmd_w0.s.dlen = rte_cpu_to_be_16(inputlen + OFF_CTRL_LEN);
|
||||
|
||||
vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
|
||||
|
||||
if (likely(iv_len)) {
|
||||
uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
|
||||
+ OFF_CTRL_LEN);
|
||||
memcpy(iv_d, iv, 16);
|
||||
}
|
||||
|
||||
/* iv offset is 0 */
|
||||
*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
|
||||
} else {
|
||||
uint32_t i, g_size_bytes, s_size_bytes;
|
||||
uint64_t dptr_dma, rptr_dma;
|
||||
sg_comp_t *gather_comp;
|
||||
sg_comp_t *scatter_comp;
|
||||
uint8_t *in_buffer;
|
||||
uint32_t *iv_d;
|
||||
|
||||
/* save space for offset and iv... */
|
||||
offset_vaddr = m_vaddr;
|
||||
offset_dma = m_dma;
|
||||
|
||||
m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
|
||||
m_dma += OFF_CTRL_LEN + iv_len;
|
||||
m_size -= OFF_CTRL_LEN + iv_len;
|
||||
|
||||
opcode.s.major |= CPT_DMA_MODE;
|
||||
|
||||
vq_cmd_w0.s.opcode = rte_cpu_to_be_16(opcode.flags);
|
||||
|
||||
/* DPTR has SG list */
|
||||
in_buffer = m_vaddr;
|
||||
dptr_dma = m_dma;
|
||||
|
||||
((uint16_t *)in_buffer)[0] = 0;
|
||||
((uint16_t *)in_buffer)[1] = 0;
|
||||
|
||||
/* TODO Add error check if space will be sufficient */
|
||||
gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
|
||||
|
||||
/*
|
||||
* Input Gather List
|
||||
*/
|
||||
i = 0;
|
||||
|
||||
/* Offset control word */
|
||||
|
||||
/* iv offset is 0 */
|
||||
*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
|
||||
|
||||
i = fill_sg_comp(gather_comp, i, offset_dma,
|
||||
OFF_CTRL_LEN + iv_len);
|
||||
|
||||
iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
|
||||
memcpy(iv_d, iv, 16);
|
||||
|
||||
/* Add input data */
|
||||
size = inputlen - iv_len;
|
||||
if (size) {
|
||||
i = fill_sg_comp_from_iov(gather_comp, i,
|
||||
params->src_iov,
|
||||
0, &size, NULL, 0);
|
||||
if (size)
|
||||
return ERR_BAD_INPUT_ARG;
|
||||
}
|
||||
((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
|
||||
g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
|
||||
|
||||
/*
|
||||
* Output Scatter List
|
||||
*/
|
||||
|
||||
i = 0;
|
||||
scatter_comp =
|
||||
(sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
|
||||
|
||||
/* IV */
|
||||
i = fill_sg_comp(scatter_comp, i,
|
||||
offset_dma + OFF_CTRL_LEN,
|
||||
iv_len);
|
||||
|
||||
/* Add output data */
|
||||
size = outputlen - iv_len;
|
||||
if (size) {
|
||||
i = fill_sg_comp_from_iov(scatter_comp, i,
|
||||
params->dst_iov, 0,
|
||||
&size, NULL, 0);
|
||||
|
||||
if (size)
|
||||
return ERR_BAD_INPUT_ARG;
|
||||
}
|
||||
((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
|
||||
s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
|
||||
|
||||
size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
|
||||
|
||||
/* This is DPTR len incase of SG mode */
|
||||
vq_cmd_w0.s.dlen = rte_cpu_to_be_16(size);
|
||||
|
||||
m_vaddr = (uint8_t *)m_vaddr + size;
|
||||
m_dma += size;
|
||||
m_size -= size;
|
||||
|
||||
/* cpt alternate completion address saved earlier */
|
||||
req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
|
||||
*req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
|
||||
rptr_dma = c_dma - 8;
|
||||
|
||||
req->ist.ei1 = dptr_dma;
|
||||
req->ist.ei2 = rptr_dma;
|
||||
}
|
||||
|
||||
/* First 16-bit swap then 64-bit swap */
|
||||
/* TODO: HACK: Reverse the vq_cmd and cpt_req bit field definitions
|
||||
* to eliminate all the swapping
|
||||
*/
|
||||
vq_cmd_w0.u64 = rte_cpu_to_be_64(vq_cmd_w0.u64);
|
||||
|
||||
/* vq command w3 */
|
||||
vq_cmd_w3.u64 = 0;
|
||||
vq_cmd_w3.s.grp = 0;
|
||||
vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
|
||||
offsetof(struct cpt_ctx, zs_ctx);
|
||||
|
||||
/* 16 byte aligned cpt res address */
|
||||
req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
|
||||
*req->completion_addr = COMPLETION_CODE_INIT;
|
||||
req->comp_baddr = c_dma;
|
||||
|
||||
/* Fill microcode part of instruction */
|
||||
req->ist.ei0 = vq_cmd_w0.u64;
|
||||
req->ist.ei3 = vq_cmd_w3.u64;
|
||||
|
||||
req->op = op;
|
||||
|
||||
*prep_req = req;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __rte_always_inline void *
|
||||
cpt_fc_dec_hmac_prep(uint32_t flags,
|
||||
uint64_t d_offs,
|
||||
@ -1243,6 +1833,9 @@ cpt_fc_dec_hmac_prep(uint32_t flags,
|
||||
if (likely(fc_type == FC_GEN)) {
|
||||
ret = cpt_dec_hmac_prep(flags, d_offs, d_lens,
|
||||
fc_params, op, &prep_req);
|
||||
} else if (fc_type == ZUC_SNOW3G) {
|
||||
ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens,
|
||||
fc_params, op, &prep_req);
|
||||
} else {
|
||||
/*
|
||||
* For AUTH_ONLY case,
|
||||
@ -1273,6 +1866,9 @@ cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
|
||||
if (likely(fc_type == FC_GEN)) {
|
||||
ret = cpt_enc_hmac_prep(flags, d_offs, d_lens,
|
||||
fc_params, op, &prep_req);
|
||||
} else if (fc_type == ZUC_SNOW3G) {
|
||||
ret = cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens,
|
||||
fc_params, op, &prep_req);
|
||||
} else {
|
||||
ret = ERR_EIO;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user