ixgbe: add access to specific device info
add function to support ethtool ops: - get_reg_length - get_regs - get_eeprom_length - get_eeprom - set_eeprom Signed-off-by: Liang-Min Larry Wang <liang-min.wang@intel.com> Acked-by: Andrew Harvey <agh@cisco.com> Acked-by: David Harton <dharton@cisco.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
This commit is contained in:
Liang-Min Larry Wang
Thomas Monjalon
parent
83c314da4c
commit
0198848a47
@ -68,6 +68,9 @@
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#include "ixgbe_ethdev.h"
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#include "ixgbe_bypass.h"
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#include "ixgbe_rxtx.h"
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#include "base/ixgbe_type.h"
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#include "base/ixgbe_phy.h"
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#include "ixgbe_regs.h"
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/*
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* High threshold controlling when to start sending XOFF frames. Must be at
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@ -91,6 +94,7 @@
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#define IXGBE_MMW_SIZE_DEFAULT 0x4
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#define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
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#define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
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/*
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* Default values for RX/TX configuration
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@ -273,6 +277,19 @@ static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
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struct ether_addr *mc_addr_set,
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uint32_t nb_mc_addr);
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static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
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static int ixgbe_get_regs(struct rte_eth_dev *dev,
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struct rte_dev_reg_info *regs);
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static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
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static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
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struct rte_dev_eeprom_info *eeprom);
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static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
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struct rte_dev_eeprom_info *eeprom);
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static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
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static int ixgbevf_get_regs(struct rte_eth_dev *dev,
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struct rte_dev_reg_info *regs);
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static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
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static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
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static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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@ -411,6 +428,11 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
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.timesync_disable = ixgbe_timesync_disable,
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.timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
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.timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
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.get_reg_length = ixgbe_get_reg_length,
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.get_reg = ixgbe_get_regs,
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.get_eeprom_length = ixgbe_get_eeprom_length,
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.get_eeprom = ixgbe_get_eeprom,
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.set_eeprom = ixgbe_set_eeprom,
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};
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/*
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@ -438,6 +460,8 @@ static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
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.mac_addr_remove = ixgbevf_remove_mac_addr,
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.set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
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.mac_addr_set = ixgbevf_set_default_mac_addr,
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.get_reg_length = ixgbevf_get_reg_length,
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.get_reg = ixgbevf_get_regs,
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};
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/**
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@ -4663,6 +4687,134 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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return 0;
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}
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static int
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ixgbe_get_reg_length(struct rte_eth_dev *dev)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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int count = 0;
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int g_ind = 0;
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const struct reg_info *reg_group;
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const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
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ixgbe_regs_mac_82598EB : ixgbe_regs_others;
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while ((reg_group = reg_set[g_ind++]))
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count += ixgbe_regs_group_count(reg_group);
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return count;
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}
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static int
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ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
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{
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int count = 0;
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int g_ind = 0;
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const struct reg_info *reg_group;
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while ((reg_group = ixgbevf_regs[g_ind++]))
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count += ixgbe_regs_group_count(reg_group);
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return count;
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}
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static int
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ixgbe_get_regs(struct rte_eth_dev *dev,
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struct rte_dev_reg_info *regs)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t *data = regs->data;
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int g_ind = 0;
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int count = 0;
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const struct reg_info *reg_group;
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const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
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ixgbe_regs_mac_82598EB : ixgbe_regs_others;
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/* Support only full register dump */
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if ((regs->length == 0) ||
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(regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
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regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
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hw->device_id;
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while ((reg_group = reg_set[g_ind++]))
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count += ixgbe_read_regs_group(dev, &data[count],
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reg_group);
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return 0;
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}
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return -ENOTSUP;
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}
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static int
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ixgbevf_get_regs(struct rte_eth_dev *dev,
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struct rte_dev_reg_info *regs)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t *data = regs->data;
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int g_ind = 0;
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int count = 0;
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const struct reg_info *reg_group;
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/* Support only full register dump */
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if ((regs->length == 0) ||
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(regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
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regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
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hw->device_id;
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while ((reg_group = ixgbevf_regs[g_ind++]))
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count += ixgbe_read_regs_group(dev, &data[count],
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reg_group);
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return 0;
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}
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return -ENOTSUP;
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}
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static int
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ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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/* Return unit is byte count */
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return hw->eeprom.word_size * 2;
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}
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static int
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ixgbe_get_eeprom(struct rte_eth_dev *dev,
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struct rte_dev_eeprom_info *in_eeprom)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
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uint16_t *data = in_eeprom->data;
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int first, length;
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first = in_eeprom->offset >> 1;
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length = in_eeprom->length >> 1;
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if ((first >= hw->eeprom.word_size) ||
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((first + length) >= hw->eeprom.word_size))
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return -EINVAL;
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in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
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return eeprom->ops.read_buffer(hw, first, length, data);
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}
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static int
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ixgbe_set_eeprom(struct rte_eth_dev *dev,
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struct rte_dev_eeprom_info *in_eeprom)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
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uint16_t *data = in_eeprom->data;
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int first, length;
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first = in_eeprom->offset >> 1;
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length = in_eeprom->length >> 1;
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if ((first >= hw->eeprom.word_size) ||
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((first + length) >= hw->eeprom.word_size))
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return -EINVAL;
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in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
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return eeprom->ops.write_buffer(hw, first, length, data);
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}
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static struct rte_driver rte_ixgbe_driver = {
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.type = PMD_PDEV,
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.init = rte_ixgbe_pmd_init,
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376
drivers/net/ixgbe/ixgbe_regs.h
Normal file
376
drivers/net/ixgbe/ixgbe_regs.h
Normal file
@ -0,0 +1,376 @@
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/*-
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* BSD LICENSE
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*
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* Copyright(c) 2015 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IXGBE_REGS_H_
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#define _IXGBE_REGS_H_
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#include "ixgbe_ethdev.h"
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struct ixgbe_hw;
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struct reg_info {
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uint32_t base_addr;
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uint32_t count;
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uint32_t stride;
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const char *name;
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} reg_info;
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static const struct reg_info ixgbe_regs_general[] = {
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{IXGBE_CTRL, 1, 1, "IXGBE_CTRL"},
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{IXGBE_STATUS, 1, 1, "IXGBE_STATUS"},
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{IXGBE_CTRL_EXT, 1, 1, "IXGBE_CTRL_EXT"},
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{IXGBE_ESDP, 1, 1, "IXGBE_ESDP"},
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{IXGBE_EODSDP, 1, 1, "IXGBE_EODSDP"},
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{IXGBE_LEDCTL, 1, 1, "IXGBE_LEDCTL"},
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{IXGBE_FRTIMER, 1, 1, "IXGBE_FRTIMER"},
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{IXGBE_TCPTIMER, 1, 1, "IXGBE_TCPTIMER"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbevf_regs_general[] = {
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{IXGBE_CTRL, 1, 1, "IXGBE_CTRL"},
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{IXGBE_STATUS, 1, 1, "IXGBE_STATUS"},
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{IXGBE_VFLINKS, 1, 1, "IXGBE_VFLINKS"},
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{IXGBE_FRTIMER, 1, 1, "IXGBE_FRTIMER"},
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{IXGBE_VFMAILBOX, 1, 1, "IXGBE_VFMAILBOX"},
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{IXGBE_VFMBMEM, 16, 4, "IXGBE_VFMBMEM"},
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{IXGBE_VFRXMEMWRAP, 1, 1, "IXGBE_VFRXMEMWRAP"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbe_regs_nvm[] = {
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{IXGBE_EEC, 1, 1, "IXGBE_EEC"},
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{IXGBE_EERD, 1, 1, "IXGBE_EERD"},
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{IXGBE_FLA, 1, 1, "IXGBE_FLA"},
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{IXGBE_EEMNGCTL, 1, 1, "IXGBE_EEMNGCTL"},
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{IXGBE_EEMNGDATA, 1, 1, "IXGBE_EEMNGDATA"},
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{IXGBE_FLMNGCTL, 1, 1, "IXGBE_FLMNGCTL"},
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{IXGBE_FLMNGDATA, 1, 1, "IXGBE_FLMNGDATA"},
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{IXGBE_FLMNGCNT, 1, 1, "IXGBE_FLMNGCNT"},
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{IXGBE_FLOP, 1, 1, "IXGBE_FLOP"},
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{IXGBE_GRC, 1, 1, "IXGBE_GRC"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbe_regs_interrupt[] = {
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{IXGBE_EICS, 1, 1, "IXGBE_EICS"},
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{IXGBE_EIMS, 1, 1, "IXGBE_EIMS"},
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{IXGBE_EIMC, 1, 1, "IXGBE_EIMC"},
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{IXGBE_EIAC, 1, 1, "IXGBE_EIAC"},
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{IXGBE_EIAM, 1, 1, "IXGBE_EIAM"},
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{IXGBE_EITR(0), 24, 4, "IXGBE_EITR"},
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{IXGBE_IVAR(0), 24, 4, "IXGBE_IVAR"},
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{IXGBE_MSIXT, 1, 1, "IXGBE_MSIXT"},
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{IXGBE_MSIXPBA, 1, 1, "IXGBE_MSIXPBA"},
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{IXGBE_PBACL(0), 1, 4, "IXGBE_PBACL"},
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{IXGBE_GPIE, 1, 1, ""},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbevf_regs_interrupt[] = {
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{IXGBE_VTEICR, 1, 1, "IXGBE_VTEICR"},
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{IXGBE_VTEICS, 1, 1, "IXGBE_VTEICS"},
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{IXGBE_VTEIMS, 1, 1, "IXGBE_VTEIMS"},
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{IXGBE_VTEIMC, 1, 1, "IXGBE_VTEIMC"},
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{IXGBE_VTEIAM, 1, 1, "IXGBE_VTEIAM"},
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{IXGBE_VTEITR(0), 2, 4, "IXGBE_VTEITR"},
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{IXGBE_VTIVAR(0), 4, 4, "IXGBE_VTIVAR"},
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{IXGBE_VTIVAR_MISC, 1, 1, "IXGBE_VTIVAR_MISC"},
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{IXGBE_VTRSCINT(0), 2, 4, "IXGBE_VTRSCINT"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbe_regs_fctl_mac_82598EB[] = {
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{IXGBE_PFCTOP, 1, 1, ""},
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{IXGBE_FCTTV(0), 4, 4, ""},
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{IXGBE_FCRTV, 1, 1, ""},
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{IXGBE_TFCS, 1, 1, ""},
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{IXGBE_FCRTL(0), 8, 8, "IXGBE_FCRTL"},
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{IXGBE_FCRTH(0), 8, 8, "IXGBE_FCRTH"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbe_regs_fctl_others[] = {
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{IXGBE_PFCTOP, 1, 1, ""},
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{IXGBE_FCTTV(0), 4, 4, ""},
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{IXGBE_FCRTV, 1, 1, ""},
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{IXGBE_TFCS, 1, 1, ""},
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{IXGBE_FCRTL_82599(0), 8, 4, "IXGBE_FCRTL"},
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{IXGBE_FCRTH_82599(0), 8, 4, "IXGBE_FCRTH"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbe_regs_rxdma[] = {
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{IXGBE_RDBAL(0), 64, 0x40, "IXGBE_RDBAL"},
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{IXGBE_RDBAH(0), 64, 0x40, "IXGBE_RDBAH"},
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{IXGBE_RDLEN(0), 64, 0x40, "IXGBE_RDLEN"},
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{IXGBE_RDH(0), 64, 0x40, "IXGBE_RDH"},
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{IXGBE_RDT(0), 64, 0x40, "IXGBE_RDT"},
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{IXGBE_RXDCTL(0), 64, 0x40, "IXGBE_RXDCTL"},
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{IXGBE_SRRCTL(0), 16, 0x4, "IXGBE_SRRCTL"},
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{IXGBE_DCA_RXCTRL(0), 16, 4, "IXGBE_DCA_RXCTRL"},
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{IXGBE_RDRXCTL, 1, 1, "IXGBE_RDRXCTL"},
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{IXGBE_RXPBSIZE(0), 8, 4, "IXGBE_RXPBSIZE"},
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{IXGBE_RXCTRL, 1, 1, "IXGBE_RXCTRL"},
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{IXGBE_DROPEN, 1, 1, "IXGBE_DROPEN"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbevf_regs_rxdma[] = {
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{IXGBE_RDBAL(0), 8, 0x40, "IXGBE_RDBAL"},
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{IXGBE_RDBAH(0), 8, 0x40, "IXGBE_RDBAH"},
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{IXGBE_RDLEN(0), 8, 0x40, "IXGBE_RDLEN"},
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{IXGBE_RDH(0), 8, 0x40, "IXGBE_RDH"},
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{IXGBE_RDT(0), 8, 0x40, "IXGBE_RDT"},
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{IXGBE_RXDCTL(0), 8, 0x40, "IXGBE_RXDCTL"},
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{IXGBE_SRRCTL(0), 8, 0x40, "IXGBE_SRRCTL"},
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{IXGBE_VFPSRTYPE, 1, 1, "IXGBE_VFPSRTYPE"},
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{IXGBE_VFRSCCTL(0), 8, 0x40, "IXGBE_VFRSCCTL"},
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{IXGBE_PVFDCA_RXCTRL(0), 8, 0x40, "IXGBE_PVFDCA_RXCTRL"},
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{IXGBE_PVFDCA_TXCTRL(0), 8, 0x40, "IXGBE_PVFDCA_TXCTRL"},
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{0, 0, 0, ""}
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};
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static const struct reg_info ixgbe_regs_rx[] = {
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{IXGBE_RXCSUM, 1, 1, "IXGBE_RXCSUM"},
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{IXGBE_RFCTL, 1, 1, "IXGBE_RFCTL"},
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{IXGBE_RAL(0), 16, 8, "IXGBE_RAL"},
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{IXGBE_RAH(0), 16, 8, "IXGBE_RAH"},
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{IXGBE_PSRTYPE(0), 1, 4, "IXGBE_PSRTYPE"},
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{IXGBE_FCTRL, 1, 1, "IXGBE_FCTRL"},
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||||
{IXGBE_VLNCTRL, 1, 1, "IXGBE_VLNCTRL"},
|
||||
{IXGBE_MCSTCTRL, 1, 1, "IXGBE_MCSTCTRL"},
|
||||
{IXGBE_MRQC, 1, 1, "IXGBE_MRQC"},
|
||||
{IXGBE_VMD_CTL, 1, 1, "IXGBE_VMD_CTL"},
|
||||
{IXGBE_IMIR(0), 8, 4, "IXGBE_IMIR"},
|
||||
{IXGBE_IMIREXT(0), 8, 4, "IXGBE_IMIREXT"},
|
||||
{IXGBE_IMIRVP, 1, 1, "IXGBE_IMIRVP"},
|
||||
{0, 0, 0, ""}
|
||||
};
|
||||
|
||||
static struct reg_info ixgbe_regs_tx[] = {
|
||||
{IXGBE_TDBAL(0), 32, 0x40, "IXGBE_TDBAL"},
|
||||
{IXGBE_TDBAH(0), 32, 0x40, "IXGBE_TDBAH"},
|
||||
{IXGBE_TDLEN(0), 32, 0x40, "IXGBE_TDLEN"},
|
||||
{IXGBE_TDH(0), 32, 0x40, "IXGBE_TDH"},
|
||||
{IXGBE_TDT(0), 32, 0x40, "IXGBE_TDT"},
|
||||
{IXGBE_TXDCTL(0), 32, 0x40, "IXGBE_TXDCTL"},
|
||||
{IXGBE_TDWBAL(0), 32, 0x40, "IXGBE_TDWBAL"},
|
||||
{IXGBE_TDWBAH(0), 32, 0x40, "IXGBE_TDWBAH"},
|
||||
{IXGBE_DTXCTL, 1, 1, "IXGBE_DTXCTL"},
|
||||
{IXGBE_DCA_TXCTRL(0), 16, 4, "IXGBE_DCA_TXCTRL"},
|
||||
{IXGBE_TXPBSIZE(0), 8, 4, "IXGBE_TXPBSIZE"},
|
||||
{IXGBE_MNGTXMAP, 1, 1, "IXGBE_MNGTXMAP"},
|
||||
{0, 0, 0, ""}
|
||||
};
|
||||
|
||||
static const struct reg_info ixgbevf_regs_tx[] = {
|
||||
{IXGBE_TDBAL(0), 4, 0x40, "IXGBE_TDBAL"},
|
||||
{IXGBE_TDBAH(0), 4, 0x40, "IXGBE_TDBAH"},
|
||||
{IXGBE_TDLEN(0), 4, 0x40, "IXGBE_TDLEN"},
|
||||
{IXGBE_TDH(0), 4, 0x40, "IXGBE_TDH"},
|
||||
{IXGBE_TDT(0), 4, 0x40, "IXGBE_TDT"},
|
||||
{IXGBE_TXDCTL(0), 4, 0x40, "IXGBE_TXDCTL"},
|
||||
{IXGBE_TDWBAL(0), 4, 0x40, "IXGBE_TDWBAL"},
|
||||
{IXGBE_TDWBAH(0), 4, 0x40, "IXGBE_TDWBAH"},
|
||||
{0, 0, 0, ""}
|
||||
};
|
||||
|
||||
static const struct reg_info ixgbe_regs_wakeup[] = {
|
||||
{IXGBE_WUC, 1, 1, "IXGBE_WUC"},
|
||||
{IXGBE_WUFC, 1, 1, "IXGBE_WUFC"},
|
||||
{IXGBE_WUS, 1, 1, "IXGBE_WUS"},
|
||||
{IXGBE_IPAV, 1, 1, "IXGBE_IPAV"},
|
||||
{IXGBE_IP4AT, 1, 1, "IXGBE_IP4AT"},
|
||||
{IXGBE_IP6AT, 1, 1, "IXGBE_IP6AT"},
|
||||
{IXGBE_WUPL, 1, 1, "IXGBE_WUPL"},
|
||||
{IXGBE_WUPM, 1, 1, "IXGBE_WUPM"},
|
||||
{IXGBE_FHFT(0), 1, 1, "IXGBE_FHFT"},
|
||||
{0, 0, 0, ""}
|
||||
};
|
||||
|
||||
static const struct reg_info ixgbe_regs_dcb[] = {
|
||||
{IXGBE_RMCS, 1, 1, "IXGBE_RMCS"},
|
||||
{IXGBE_DPMCS, 1, 1, "IXGBE_DPMCS"},
|
||||
{IXGBE_PDPMCS, 1, 1, "IXGBE_PDPMCS"},
|
||||
{IXGBE_RUPPBMR, 1, 1, "IXGBE_RUPPBMR"},
|
||||
{IXGBE_RT2CR(0), 8, 4, "IXGBE_RT2CR"},
|
||||
{IXGBE_RT2SR(0), 8, 4, "IXGBE_RT2SR"},
|
||||
{IXGBE_TDTQ2TCCR(0), 8, 0x40, "IXGBE_TDTQ2TCCR"},
|
||||
{IXGBE_TDTQ2TCSR(0), 8, 0x40, "IXGBE_TDTQ2TCSR"},
|
||||
{IXGBE_TDPT2TCCR(0), 8, 4, "IXGBE_TDPT2TCCR"},
|
||||
{IXGBE_TDPT2TCSR(0), 8, 4, "IXGBE_TDPT2TCSR"},
|
||||
{0, 0, 0, ""}
|
||||
};
|
||||
|
||||
static const struct reg_info ixgbe_regs_mac[] = {
|
||||
{IXGBE_PCS1GCFIG, 1, 1, "IXGBE_PCS1GCFIG"},
|
||||
{IXGBE_PCS1GLCTL, 1, 1, "IXGBE_PCS1GLCTL"},
|
||||
{IXGBE_PCS1GLSTA, 1, 1, "IXGBE_PCS1GLSTA"},
|
||||
{IXGBE_PCS1GDBG0, 1, 1, "IXGBE_PCS1GDBG0"},
|
||||
{IXGBE_PCS1GDBG1, 1, 1, "IXGBE_PCS1GDBG1"},
|
||||
{IXGBE_PCS1GANA, 1, 1, "IXGBE_PCS1GANA"},
|
||||
{IXGBE_PCS1GANLP, 1, 1, "IXGBE_PCS1GANLP"},
|
||||
{IXGBE_PCS1GANNP, 1, 1, "IXGBE_PCS1GANNP"},
|
||||
{IXGBE_PCS1GANLPNP, 1, 1, "IXGBE_PCS1GANLPNP"},
|
||||
{IXGBE_HLREG0, 1, 1, "IXGBE_HLREG0"},
|
||||
{IXGBE_HLREG1, 1, 1, "IXGBE_HLREG1"},
|
||||
{IXGBE_PAP, 1, 1, "IXGBE_PAP"},
|
||||
{IXGBE_MACA, 1, 1, "IXGBE_MACA"},
|
||||
{IXGBE_APAE, 1, 1, "IXGBE_APAE"},
|
||||
{IXGBE_ARD, 1, 1, "IXGBE_ARD"},
|
||||
{IXGBE_AIS, 1, 1, "IXGBE_AIS"},
|
||||
{IXGBE_MSCA, 1, 1, "IXGBE_MSCA"},
|
||||
{IXGBE_MSRWD, 1, 1, "IXGBE_MSRWD"},
|
||||
{IXGBE_MLADD, 1, 1, "IXGBE_MLADD"},
|
||||
{IXGBE_MHADD, 1, 1, "IXGBE_MHADD"},
|
||||
{IXGBE_TREG, 1, 1, "IXGBE_TREG"},
|
||||
{IXGBE_PCSS1, 1, 1, "IXGBE_PCSS1"},
|
||||
{IXGBE_PCSS2, 1, 1, "IXGBE_PCSS2"},
|
||||
{IXGBE_XPCSS, 1, 1, "IXGBE_XPCSS"},
|
||||
{IXGBE_SERDESC, 1, 1, "IXGBE_SERDESC"},
|
||||
{IXGBE_MACS, 1, 1, "IXGBE_MACS"},
|
||||
{IXGBE_AUTOC, 1, 1, "IXGBE_AUTOC"},
|
||||
{IXGBE_LINKS, 1, 1, "IXGBE_LINKS"},
|
||||
{IXGBE_AUTOC2, 1, 1, "IXGBE_AUTOC2"},
|
||||
{IXGBE_AUTOC3, 1, 1, "IXGBE_AUTOC3"},
|
||||
{IXGBE_ANLP1, 1, 1, "IXGBE_ANLP1"},
|
||||
{IXGBE_ANLP2, 1, 1, "IXGBE_ANLP2"},
|
||||
{IXGBE_ATLASCTL, 1, 1, "IXGBE_ATLASCTL"},
|
||||
{0, 0, 0, ""}
|
||||
};
|
||||
|
||||
static const struct reg_info ixgbe_regs_diagnostic[] = {
|
||||
{IXGBE_RDSTATCTL, 1, 1, "IXGBE_RDSTATCTL"},
|
||||
{IXGBE_RDSTAT(0), 8, 4, "IXGBE_RDSTAT"},
|
||||
{IXGBE_RDHMPN, 1, 1, "IXGBE_RDHMPN"},
|
||||
{IXGBE_RIC_DW(0), 4, 4, "IXGBE_RIC_DW"},
|
||||
{IXGBE_RDPROBE, 1, 1, "IXGBE_RDPROBE"},
|
||||
{IXGBE_TDHMPN, 1, 1, "IXGBE_TDHMPN"},
|
||||
{IXGBE_TIC_DW(0), 4, 4, "IXGBE_TIC_DW"},
|
||||
{IXGBE_TDPROBE, 1, 1, "IXGBE_TDPROBE"},
|
||||
{IXGBE_TXBUFCTRL, 1, 1, "IXGBE_TXBUFCTRL"},
|
||||
{IXGBE_TXBUFDATA0, 1, 1, "IXGBE_TXBUFDATA0"},
|
||||
{IXGBE_TXBUFDATA1, 1, 1, "IXGBE_TXBUFDATA1"},
|
||||
{IXGBE_TXBUFDATA2, 1, 1, "IXGBE_TXBUFDATA2"},
|
||||
{IXGBE_TXBUFDATA3, 1, 1, "IXGBE_TXBUFDATA3"},
|
||||
{IXGBE_RXBUFCTRL, 1, 1, "IXGBE_RXBUFCTRL"},
|
||||
{IXGBE_RXBUFDATA0, 1, 1, "IXGBE_RXBUFDATA0"},
|
||||
{IXGBE_RXBUFDATA1, 1, 1, "IXGBE_RXBUFDATA1"},
|
||||
{IXGBE_RXBUFDATA2, 1, 1, "IXGBE_RXBUFDATA2"},
|
||||
{IXGBE_RXBUFDATA3, 1, 1, "IXGBE_RXBUFDATA3"},
|
||||
{IXGBE_PCIE_DIAG(0), 8, 4, ""},
|
||||
{IXGBE_RFVAL, 1, 1, "IXGBE_RFVAL"},
|
||||
{IXGBE_MDFTC1, 1, 1, "IXGBE_MDFTC1"},
|
||||
{IXGBE_MDFTC2, 1, 1, "IXGBE_MDFTC2"},
|
||||
{IXGBE_MDFTFIFO1, 1, 1, "IXGBE_MDFTFIFO1"},
|
||||
{IXGBE_MDFTFIFO2, 1, 1, "IXGBE_MDFTFIFO2"},
|
||||
{IXGBE_MDFTS, 1, 1, "IXGBE_MDFTS"},
|
||||
{IXGBE_PCIEECCCTL, 1, 1, "IXGBE_PCIEECCCTL"},
|
||||
{IXGBE_PBTXECC, 1, 1, "IXGBE_PBTXECC"},
|
||||
{IXGBE_PBRXECC, 1, 1, "IXGBE_PBRXECC"},
|
||||
{IXGBE_MFLCN, 1, 1, "IXGBE_MFLCN"},
|
||||
{0, 0, 0, ""},
|
||||
};
|
||||
|
||||
/* PF registers */
|
||||
static const struct reg_info *ixgbe_regs_others[] = {
|
||||
ixgbe_regs_general,
|
||||
ixgbe_regs_nvm, ixgbe_regs_interrupt,
|
||||
ixgbe_regs_fctl_others,
|
||||
ixgbe_regs_rxdma,
|
||||
ixgbe_regs_rx,
|
||||
ixgbe_regs_tx,
|
||||
ixgbe_regs_wakeup,
|
||||
ixgbe_regs_dcb,
|
||||
ixgbe_regs_mac,
|
||||
ixgbe_regs_diagnostic,
|
||||
NULL};
|
||||
|
||||
static const struct reg_info *ixgbe_regs_mac_82598EB[] = {
|
||||
ixgbe_regs_general,
|
||||
ixgbe_regs_nvm,
|
||||
ixgbe_regs_interrupt,
|
||||
ixgbe_regs_fctl_mac_82598EB,
|
||||
ixgbe_regs_rxdma,
|
||||
ixgbe_regs_rx,
|
||||
ixgbe_regs_tx,
|
||||
ixgbe_regs_wakeup,
|
||||
ixgbe_regs_dcb,
|
||||
ixgbe_regs_mac,
|
||||
ixgbe_regs_diagnostic,
|
||||
NULL};
|
||||
|
||||
/* VF registers */
|
||||
static const struct reg_info *ixgbevf_regs[] = {
|
||||
ixgbevf_regs_general,
|
||||
ixgbevf_regs_interrupt,
|
||||
ixgbevf_regs_rxdma,
|
||||
ixgbevf_regs_tx,
|
||||
NULL};
|
||||
|
||||
static inline int
|
||||
ixgbe_read_regs(struct ixgbe_hw *hw, const struct reg_info *reg,
|
||||
uint32_t *reg_buf)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < reg->count; i++)
|
||||
reg_buf[i] = IXGBE_READ_REG(hw,
|
||||
reg->base_addr + i * reg->stride);
|
||||
return reg->count;
|
||||
};
|
||||
|
||||
static inline int
|
||||
ixgbe_regs_group_count(const struct reg_info *regs)
|
||||
{
|
||||
int count = 0;
|
||||
int i = 0;
|
||||
|
||||
while (regs[i].count)
|
||||
count += regs[i++].count;
|
||||
return count;
|
||||
};
|
||||
|
||||
static inline int
|
||||
ixgbe_read_regs_group(struct rte_eth_dev *dev, uint32_t *reg_buf,
|
||||
const struct reg_info *regs)
|
||||
{
|
||||
int count = 0;
|
||||
int i = 0;
|
||||
struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
||||
|
||||
while (regs[i].count)
|
||||
count += ixgbe_read_regs(hw, ®s[i++], ®_buf[count]);
|
||||
return count;
|
||||
};
|
||||
|
||||
#endif /* _IXGBE_REGS_H_ */
|
||||
Loading…
Reference in New Issue
Block a user