net/idpf: support basic Rx data path
Add basic Rx support in split queue mode and single queue mode. Signed-off-by: Beilei Xing <beilei.xing@intel.com> Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
This commit is contained in:
Junfeng Guo
Thomas Monjalon
parent
f163a00f2a
commit
027cdcafe8
@ -348,6 +348,8 @@ idpf_dev_start(struct rte_eth_dev *dev)
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goto err_mtu;
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}
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idpf_set_rx_function(dev);
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ret = idpf_vc_ena_dis_vport(vport, true);
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if (ret != 0) {
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PMD_DRV_LOG(ERR, "Failed to enable vport");
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@ -1208,3 +1208,276 @@ idpf_stop_queues(struct rte_eth_dev *dev)
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PMD_DRV_LOG(WARNING, "Fail to stop Tx queue %d", i);
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}
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}
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static void
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idpf_split_rx_bufq_refill(struct idpf_rx_queue *rx_bufq)
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{
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volatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_ring;
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volatile struct virtchnl2_splitq_rx_buf_desc *rx_buf_desc;
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uint16_t nb_refill = rx_bufq->rx_free_thresh;
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uint16_t nb_desc = rx_bufq->nb_rx_desc;
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uint16_t next_avail = rx_bufq->rx_tail;
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struct rte_mbuf *nmb[rx_bufq->rx_free_thresh];
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struct rte_eth_dev *dev;
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uint64_t dma_addr;
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uint16_t delta;
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int i;
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if (rx_bufq->nb_rx_hold < rx_bufq->rx_free_thresh)
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return;
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rx_buf_ring = rx_bufq->rx_ring;
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delta = nb_desc - next_avail;
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if (unlikely(delta < nb_refill)) {
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if (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, delta) == 0)) {
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for (i = 0; i < delta; i++) {
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rx_buf_desc = &rx_buf_ring[next_avail + i];
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rx_bufq->sw_ring[next_avail + i] = nmb[i];
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dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));
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rx_buf_desc->hdr_addr = 0;
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rx_buf_desc->pkt_addr = dma_addr;
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}
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nb_refill -= delta;
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next_avail = 0;
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rx_bufq->nb_rx_hold -= delta;
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} else {
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dev = &rte_eth_devices[rx_bufq->port_id];
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dev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;
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PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u queue_id=%u",
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rx_bufq->port_id, rx_bufq->queue_id);
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return;
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}
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}
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if (nb_desc - next_avail >= nb_refill) {
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if (likely(rte_pktmbuf_alloc_bulk(rx_bufq->mp, nmb, nb_refill) == 0)) {
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for (i = 0; i < nb_refill; i++) {
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rx_buf_desc = &rx_buf_ring[next_avail + i];
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rx_bufq->sw_ring[next_avail + i] = nmb[i];
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dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb[i]));
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rx_buf_desc->hdr_addr = 0;
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rx_buf_desc->pkt_addr = dma_addr;
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}
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next_avail += nb_refill;
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rx_bufq->nb_rx_hold -= nb_refill;
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} else {
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dev = &rte_eth_devices[rx_bufq->port_id];
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dev->data->rx_mbuf_alloc_failed += nb_desc - next_avail;
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PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u queue_id=%u",
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rx_bufq->port_id, rx_bufq->queue_id);
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}
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}
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IDPF_PCI_REG_WRITE(rx_bufq->qrx_tail, next_avail);
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rx_bufq->rx_tail = next_avail;
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}
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uint16_t
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idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts)
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{
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volatile struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc_ring;
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volatile struct virtchnl2_rx_flex_desc_adv_nic_3 *rx_desc;
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uint16_t pktlen_gen_bufq_id;
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struct idpf_rx_queue *rxq;
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struct rte_mbuf *rxm;
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uint16_t rx_id_bufq1;
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uint16_t rx_id_bufq2;
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uint16_t pkt_len;
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uint16_t bufq_id;
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uint16_t gen_id;
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uint16_t rx_id;
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uint16_t nb_rx;
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nb_rx = 0;
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rxq = rx_queue;
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if (unlikely(rxq == NULL) || unlikely(!rxq->q_started))
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return nb_rx;
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rx_id = rxq->rx_tail;
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rx_id_bufq1 = rxq->bufq1->rx_next_avail;
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rx_id_bufq2 = rxq->bufq2->rx_next_avail;
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rx_desc_ring = rxq->rx_ring;
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while (nb_rx < nb_pkts) {
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rx_desc = &rx_desc_ring[rx_id];
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pktlen_gen_bufq_id =
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rte_le_to_cpu_16(rx_desc->pktlen_gen_bufq_id);
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gen_id = (pktlen_gen_bufq_id &
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VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_M) >>
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VIRTCHNL2_RX_FLEX_DESC_ADV_GEN_S;
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if (gen_id != rxq->expected_gen_id)
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break;
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pkt_len = (pktlen_gen_bufq_id &
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VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_M) >>
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VIRTCHNL2_RX_FLEX_DESC_ADV_LEN_PBUF_S;
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if (pkt_len == 0)
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PMD_RX_LOG(ERR, "Packet length is 0");
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rx_id++;
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if (unlikely(rx_id == rxq->nb_rx_desc)) {
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rx_id = 0;
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rxq->expected_gen_id ^= 1;
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}
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bufq_id = (pktlen_gen_bufq_id &
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VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_M) >>
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VIRTCHNL2_RX_FLEX_DESC_ADV_BUFQ_ID_S;
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if (bufq_id == 0) {
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rxm = rxq->bufq1->sw_ring[rx_id_bufq1];
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rx_id_bufq1++;
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if (unlikely(rx_id_bufq1 == rxq->bufq1->nb_rx_desc))
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rx_id_bufq1 = 0;
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rxq->bufq1->nb_rx_hold++;
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} else {
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rxm = rxq->bufq2->sw_ring[rx_id_bufq2];
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rx_id_bufq2++;
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if (unlikely(rx_id_bufq2 == rxq->bufq2->nb_rx_desc))
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rx_id_bufq2 = 0;
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rxq->bufq2->nb_rx_hold++;
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}
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rxm->pkt_len = pkt_len;
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rxm->data_len = pkt_len;
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rxm->data_off = RTE_PKTMBUF_HEADROOM;
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rxm->next = NULL;
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rxm->nb_segs = 1;
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rxm->port = rxq->port_id;
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rx_pkts[nb_rx++] = rxm;
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}
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if (nb_rx > 0) {
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rxq->rx_tail = rx_id;
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if (rx_id_bufq1 != rxq->bufq1->rx_next_avail)
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rxq->bufq1->rx_next_avail = rx_id_bufq1;
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if (rx_id_bufq2 != rxq->bufq2->rx_next_avail)
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rxq->bufq2->rx_next_avail = rx_id_bufq2;
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idpf_split_rx_bufq_refill(rxq->bufq1);
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idpf_split_rx_bufq_refill(rxq->bufq2);
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}
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return nb_rx;
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}
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static inline void
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idpf_update_rx_tail(struct idpf_rx_queue *rxq, uint16_t nb_hold,
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uint16_t rx_id)
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{
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nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
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if (nb_hold > rxq->rx_free_thresh) {
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PMD_RX_LOG(DEBUG,
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"port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
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rxq->port_id, rxq->queue_id, rx_id, nb_hold);
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rx_id = (uint16_t)((rx_id == 0) ?
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(rxq->nb_rx_desc - 1) : (rx_id - 1));
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IDPF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
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nb_hold = 0;
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}
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rxq->nb_rx_hold = nb_hold;
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}
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uint16_t
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idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts)
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{
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volatile union virtchnl2_rx_desc *rx_ring;
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volatile union virtchnl2_rx_desc *rxdp;
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union virtchnl2_rx_desc rxd;
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struct idpf_rx_queue *rxq;
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uint16_t rx_id, nb_hold;
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struct rte_eth_dev *dev;
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uint16_t rx_packet_len;
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struct rte_mbuf *rxm;
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struct rte_mbuf *nmb;
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uint16_t rx_status0;
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uint64_t dma_addr;
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uint16_t nb_rx;
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nb_rx = 0;
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nb_hold = 0;
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rxq = rx_queue;
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if (unlikely(rxq == NULL) || unlikely(!rxq->q_started))
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return nb_rx;
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rx_id = rxq->rx_tail;
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rx_ring = rxq->rx_ring;
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while (nb_rx < nb_pkts) {
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rxdp = &rx_ring[rx_id];
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rx_status0 = rte_le_to_cpu_16(rxdp->flex_nic_wb.status_error0);
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/* Check the DD bit first */
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if ((rx_status0 & (1 << VIRTCHNL2_RX_FLEX_DESC_STATUS0_DD_S)) == 0)
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break;
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nmb = rte_mbuf_raw_alloc(rxq->mp);
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if (unlikely(nmb == NULL)) {
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dev = &rte_eth_devices[rxq->port_id];
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dev->data->rx_mbuf_alloc_failed++;
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PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
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"queue_id=%u", rxq->port_id, rxq->queue_id);
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break;
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}
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rxd = *rxdp; /* copy descriptor in ring to temp variable*/
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nb_hold++;
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rxm = rxq->sw_ring[rx_id];
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rxq->sw_ring[rx_id] = nmb;
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rx_id++;
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if (unlikely(rx_id == rxq->nb_rx_desc))
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rx_id = 0;
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/* Prefetch next mbuf */
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rte_prefetch0(rxq->sw_ring[rx_id]);
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/* When next RX descriptor is on a cache line boundary,
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* prefetch the next 4 RX descriptors and next 8 pointers
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* to mbufs.
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*/
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if ((rx_id & 0x3) == 0) {
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rte_prefetch0(&rx_ring[rx_id]);
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rte_prefetch0(rxq->sw_ring[rx_id]);
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}
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dma_addr =
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rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
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rxdp->read.hdr_addr = 0;
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rxdp->read.pkt_addr = dma_addr;
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rx_packet_len = (rte_cpu_to_le_16(rxd.flex_nic_wb.pkt_len) &
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VIRTCHNL2_RX_FLEX_DESC_PKT_LEN_M);
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rxm->data_off = RTE_PKTMBUF_HEADROOM;
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rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
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rxm->nb_segs = 1;
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rxm->next = NULL;
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rxm->pkt_len = rx_packet_len;
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rxm->data_len = rx_packet_len;
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rxm->port = rxq->port_id;
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rx_pkts[nb_rx++] = rxm;
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}
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rxq->rx_tail = rx_id;
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idpf_update_rx_tail(rxq, nb_hold, rx_id);
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return nb_rx;
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}
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void
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idpf_set_rx_function(struct rte_eth_dev *dev)
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{
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struct idpf_vport *vport = dev->data->dev_private;
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if (vport->rxq_model == VIRTCHNL2_QUEUE_MODEL_SPLIT)
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dev->rx_pkt_burst = idpf_splitq_recv_pkts;
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else
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dev->rx_pkt_burst = idpf_singleq_recv_pkts;
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}
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@ -133,6 +133,11 @@ int idpf_tx_queue_init(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int idpf_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int idpf_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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void idpf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
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uint16_t idpf_singleq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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uint16_t idpf_splitq_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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void idpf_stop_queues(struct rte_eth_dev *dev);
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void idpf_set_rx_function(struct rte_eth_dev *dev);
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#endif /* _IDPF_RXTX_H_ */
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