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net/octeontx2: support custom L2 header

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This patch adds SDP packet parsing support with custom L2 header,
adds support to include a field from custom header for flow tag
generation.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Satheesh Paul 2020-04-06 12:13:03 +05:30 committed by Ferruh Yigit
parent b372fff7d4
commit 0342232aa4
6 changed files with 20 additions and 3 deletions
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2
doc/guides/nics/octeontx2.rst
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@ -178,7 +178,7 @@ Runtime Config Options
With the above configuration, higig2 will be enabled on that port and the
traffic on this port should be higig2 traffic only. Supported switch header
types are "higig2" and "dsa".
types are "higig2", "dsa" and "chlen90b".
- ``RSS tag as XOR`` (default ``0``)

2
drivers/common/octeontx2/hw/otx2_npc.h
View File

@ -31,6 +31,7 @@
(0x80008ull | (uint64_t)(a) << 6)
#define NPC_AF_PKINDX_CPI_DEFX(a, b) \
(0x80020ull | (uint64_t)(a) << 6 | (uint64_t)(b) << 3)
#define NPC_AF_CHLEN90B_PKIND (0x3bull)
#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \
(0x100000ull | (uint64_t)(a) << 14 | (uint64_t)(b) << 6 | \
(uint64_t)(c) << 3)
@ -184,6 +185,7 @@ enum npc_kpu_la_ltype {
NPC_LT_LA_IH_2_ETHER,
NPC_LT_LA_HIGIG2_ETHER,
NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
NPC_LT_LA_CH_LEN_90B_ETHER, /* Custom L2 header of length 90 bytes */
};
enum npc_kpu_lb_ltype {

4
drivers/common/octeontx2/otx2_mbox.h
View File

@ -90,7 +90,7 @@ struct mbox_msghdr {
#define OTX2_MBOX_RSP_SIG (0xbeef)
/* Signature, for validating corrupted msgs */
uint16_t __otx2_io sig;
#define OTX2_MBOX_VERSION (0x0005)
#define OTX2_MBOX_VERSION (0x0006)
/* Version of msg's structure for this ID */
uint16_t __otx2_io ver;
/* Offset of next msg within mailbox region */
@ -341,6 +341,7 @@ struct npc_set_pkind {
#define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
#define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
#define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
#define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3)
#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
uint64_t __otx2_io mode;
#define PKIND_TX BIT_ULL(0)
@ -929,6 +930,7 @@ struct nix_rss_flowkey_cfg {
#define FLOW_KEY_TYPE_INNR_UDP BIT(15)
#define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
#define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
#define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
#define FLOW_KEY_TYPE_L4_DST BIT(28)
#define FLOW_KEY_TYPE_L4_SRC BIT(29)
#define FLOW_KEY_TYPE_L3_DST BIT(30)

6
drivers/net/octeontx2/otx2_ethdev.c
View File

@ -112,6 +112,12 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
if (dev->npc_flow.switch_header_type == 0)
return 0;
if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B &&
!otx2_dev_is_sdp(dev)) {
otx2_err("chlen90b is not supported on non-SDP device");
return -EINVAL;
}
/* Notify AF about higig2 config */
req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
req->mode = dev->npc_flow.switch_header_type;

4
drivers/net/octeontx2/otx2_ethdev_devargs.c
View File

@ -113,6 +113,8 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)
if (strcmp(value, "dsa") == 0)
*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EDSA;
if (strcmp(value, "chlen90b") == 0)
*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_LEN_90B;
return 0;
}
@ -185,5 +187,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_octeontx2,
OTX2_MAX_SQB_COUNT "=<8-512>"
OTX2_FLOW_PREALLOC_SIZE "=<1-32>"
OTX2_FLOW_MAX_PRIORITY "=<1-32>"
OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa>"
OTX2_SWITCH_HEADER_TYPE "=<higig2|dsa|chlen90b>"
OTX2_RSS_TAG_AS_XOR "=1");

5
drivers/net/octeontx2/otx2_rss.c
View File

@ -210,6 +210,11 @@ otx2_rss_ethdev_to_nix(struct otx2_eth_dev *dev, uint64_t ethdev_rss,
dev->rss_info.nix_rss = ethdev_rss;
if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B) {
flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
}
if (ethdev_rss & ETH_RSS_L3_SRC_ONLY)
flowkey_cfg |= FLOW_KEY_TYPE_L3_SRC;