common/mlx5: extend DevX HCA attributes query
Extend DevX API mlx5_devx_cmd_query_hca_attr() to report on max number of available objects including: CQ, QP, PD, SRQ. Signed-off-by: Tal Shnaiderman <talshn@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
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@ -720,6 +720,14 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
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attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,
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general_obj_types) &
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MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
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attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
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attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
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attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
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attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
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attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
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attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
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attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
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attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
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if (attr->qos.sup) {
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MLX5_SET(query_hca_cap_in, in, op_mod,
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MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
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@ -834,6 +842,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
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attr->tunnel_stateless_gtp = MLX5_GET
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(per_protocol_networking_offload_caps,
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hcattr, tunnel_stateless_gtp);
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attr->rss_ind_tbl_cap = MLX5_GET
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(per_protocol_networking_offload_caps,
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hcattr, rss_ind_tbl_cap);
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if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
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return 0;
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if (attr->eth_virt) {
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@ -117,6 +117,15 @@ struct mlx5_hca_attr {
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uint32_t log_max_ft_sampler_num:8;
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struct mlx5_hca_qos_attr qos;
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struct mlx5_hca_vdpa_attr vdpa;
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int log_max_qp_sz;
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int log_max_cq_sz;
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int log_max_qp;
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int log_max_cq;
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uint32_t log_max_pd;
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uint32_t log_max_mrw_sz;
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uint32_t log_max_srq;
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uint32_t log_max_srq_sz;
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uint32_t rss_ind_tbl_cap;
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};
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struct mlx5_devx_wq_attr {
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@ -495,7 +504,6 @@ struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
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__rte_internal
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int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
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struct mlx5_devx_virtio_q_couners_attr *attr);
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__rte_internal
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struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
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uint32_t pd);
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@ -665,6 +665,7 @@ typedef uint8_t u8;
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#define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
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__mlx5_64_off(typ, fld)))
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#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
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#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
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struct mlx5_ifc_fte_match_set_misc_bits {
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u8 gre_c_present[0x1];
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