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net/cxgbe: add support to run Chelsio T6 cards

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Add code to detect and run T6 devices.  Update PCI ID Device table
with Chelsio T6 device ids and update documentation.

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
This commit is contained in:
Rahul Lakkireddy 2017-05-27 09:16:16 +05:30 committed by Ferruh Yigit
parent 0362b7294d
commit 04868e5bfd
8 changed files with 115 additions and 26 deletions
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41
doc/guides/nics/cxgbe.rst
View File

@ -1,5 +1,5 @@
.. BSD LICENSE
Copyright 2015 Chelsio Communications.
Copyright 2015-2017 Chelsio Communications.
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -32,8 +32,8 @@ CXGBE Poll Mode Driver
======================
The CXGBE PMD (**librte_pmd_cxgbe**) provides poll mode driver support
for **Chelsio T5** 10/40 Gbps family of adapters. CXGBE PMD has support
for the latest Linux and FreeBSD operating systems.
for **Chelsio Terminator** 10/25/40/100 Gbps family of adapters. CXGBE PMD
has support for the latest Linux and FreeBSD operating systems.
More information can be found at `Chelsio Communications Official Website
<http://www.chelsio.com>`_.
@ -55,9 +55,10 @@ CXGBE PMD has support for:
Limitations
-----------
The Chelsio T5 devices provide two/four ports but expose a single PCI bus
address, thus, librte_pmd_cxgbe registers itself as a
PCI driver that allocates one Ethernet device per detected port.
The Chelsio Terminator series of devices provide two/four ports but
expose a single PCI bus address, thus, librte_pmd_cxgbe registers
itself as a PCI driver that allocates one Ethernet device per detected
port.
For this reason, one cannot whitelist/blacklist a single port without
whitelisting/blacklisting the other ports on the same device.
@ -70,10 +71,16 @@ Supported Chelsio T5 NICs
- 40G NICs: T580-CR, T580-LP-CR, T580-SO-CR
- Other T5 NICs: T522-CR
Supported Chelsio T6 NICs
-------------------------
- 25G NICs: T6425-CR, T6225-CR, T6225-LL-CR, T6225-SO-CR
- 100G NICs: T62100-CR, T62100-LP-CR, T62100-SO-CR
Prerequisites
-------------
- Requires firmware version **1.13.32.0** and higher. Visit
- Requires firmware version **1.16.43.0** and higher. Visit
`Chelsio Download Center <http://service.chelsio.com>`_ to get latest firmware
bundled with the latest Chelsio Unified Wire package.
@ -197,12 +204,12 @@ Unified Wire package for Linux operating system are as follows:
.. code-block:: console
firmware-version: 1.13.32.0, TP 0.1.4.8
firmware-version: 1.16.43.0, TP 0.1.4.9
Running testpmd
~~~~~~~~~~~~~~~
This section demonstrates how to launch **testpmd** with Chelsio T5
This section demonstrates how to launch **testpmd** with Chelsio
devices managed by librte_pmd_cxgbe in Linux operating system.
#. Load the kernel module:
@ -226,7 +233,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system.
.. note::
Both the interfaces of a Chelsio T5 2-port adapter are bound to the
Both the interfaces of a Chelsio 2-port adapter are bound to the
same PCI bus address.
#. Unload the kernel module:
@ -243,7 +250,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system.
.. note::
Currently, CXGBE PMD only supports the binding of PF4 for Chelsio T5 NICs.
Currently, CXGBE PMD only supports the binding of PF4 for Chelsio NICs.
Example output:
@ -255,7 +262,7 @@ devices managed by librte_pmd_cxgbe in Linux operating system.
EAL: PCI memory mapped at 0x7fd7c0200000
EAL: PCI memory mapped at 0x7fd77cdfd000
EAL: PCI memory mapped at 0x7fd7c10b7000
PMD: rte_cxgbe_pmd: fw: 1.13.32.0, TP: 0.1.4.8
PMD: rte_cxgbe_pmd: fw: 1.16.43.0, TP: 0.1.4.9
PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter
Interactive-mode selected
Configuring Port 0 (socket 0)
@ -339,12 +346,12 @@ Unified Wire package for FreeBSD operating system are as follows:
.. code-block:: console
dev.t5nex.0.firmware_version: 1.13.32.0
dev.t5nex.0.firmware_version: 1.16.43.0
Running testpmd
~~~~~~~~~~~~~~~
This section demonstrates how to launch **testpmd** with Chelsio T5
This section demonstrates how to launch **testpmd** with Chelsio
devices managed by librte_pmd_cxgbe in FreeBSD operating system.
#. Change to DPDK source directory where the target has been compiled in
@ -413,7 +420,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system.
.. note::
Both the interfaces of a Chelsio T5 2-port adapter are bound to the
Both the interfaces of a Chelsio 2-port adapter are bound to the
same PCI bus address.
#. Unload the kernel module:
@ -433,7 +440,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system.
.. note::
Currently, CXGBE PMD only supports the binding of PF4 for Chelsio T5 NICs.
Currently, CXGBE PMD only supports the binding of PF4 for Chelsio NICs.
#. Load nic_uio kernel driver:
@ -457,7 +464,7 @@ devices managed by librte_pmd_cxgbe in FreeBSD operating system.
EAL: PCI memory mapped at 0x8007ec000
EAL: PCI memory mapped at 0x842800000
EAL: PCI memory mapped at 0x80086c000
PMD: rte_cxgbe_pmd: fw: 1.13.32.0, TP: 0.1.4.8
PMD: rte_cxgbe_pmd: fw: 1.16.43.0, TP: 0.1.4.9
PMD: rte_cxgbe_pmd: Coming up as MASTER: Initializing adapter
Interactive-mode selected
Configuring Port 0 (socket 0)

4
doc/guides/rel_notes/release_17_08.rst
View File

@ -47,6 +47,10 @@ New Features
and inner Ethernet, VLAN, IPv4, IPv6, UDP and TCP pattern items with QUEUE,
MARK, FLAG and VOID actions for ingress traffic.
* **Added support for Chelsio T6 family of adapters**
CXGBE PMD updated to run Chelsio T6 family of adapters.
Resolved Issues
---------------

3
drivers/net/cxgbe/base/common.h
View File

@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2014-2016 Chelsio Communications.
* Copyright(c) 2014-2017 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -385,6 +385,7 @@ void t4_reset_link_config(struct adapter *adap, int idx);
int t4_get_fw_version(struct adapter *adapter, u32 *vers);
int t4_get_tp_version(struct adapter *adapter, u32 *vers);
int t4_get_flash_params(struct adapter *adapter);
int t4_get_chip_type(struct adapter *adap, int ver);
int t4_prep_adapter(struct adapter *adapter);
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
int t4_init_rss_mode(struct adapter *adap, int mbox);

11
drivers/net/cxgbe/base/t4_chip_type.h
View File

@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2014-2015 Chelsio Communications.
* Copyright(c) 2014-2017 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -49,6 +49,7 @@
#define CHELSIO_T4 0x4
#define CHELSIO_T5 0x5
#define CHELSIO_T6 0x6
#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
@ -64,6 +65,10 @@ enum chip_type {
T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
T5_FIRST_REV = T5_A0,
T5_LAST_REV = T5_A1,
T6_A0 = CHELSIO_CHIP_CODE(CHELSIO_T6, 0),
T6_FIRST_REV = T6_A0,
T6_LAST_REV = T6_A0,
};
static inline int is_t4(enum chip_type chip)
@ -76,4 +81,8 @@ static inline int is_t5(enum chip_type chip)
return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
}
static inline int is_t6(enum chip_type chip)
{
return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6);
}
#endif /* __T4_CHIP_TYPE_H__ */

46
drivers/net/cxgbe/base/t4_hw.c
View File

@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2014-2016 Chelsio Communications.
* Copyright(c) 2014-2017 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -2044,7 +2044,9 @@ int t4_flash_cfg_addr(struct adapter *adapter)
void t4_intr_enable(struct adapter *adapter)
{
u32 val = 0;
u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
@ -2069,7 +2071,9 @@ void t4_intr_enable(struct adapter *adapter)
*/
void t4_intr_disable(struct adapter *adapter)
{
u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
@ -3369,6 +3373,33 @@ static void set_pcie_completion_timeout(struct adapter *adapter,
}
}
/**
* t4_get_chip_type - Determine chip type from device ID
* @adap: the adapter
* @ver: adapter version
*/
int t4_get_chip_type(struct adapter *adap, int ver)
{
enum chip_type chip = 0;
u32 pl_rev = G_REV(t4_read_reg(adap, A_PL_REV));
/* Retrieve adapter's device ID */
switch (ver) {
case CHELSIO_T5:
chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
break;
case CHELSIO_T6:
chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
break;
default:
dev_err(adap, "Device %d is not supported\n",
adap->params.pci.device_id);
return -EINVAL;
}
return chip;
}
/**
* t4_prep_adapter - prepare SW and HW for operation
* @adapter: the adapter
@ -3406,6 +3437,15 @@ int t4_prep_adapter(struct adapter *adapter)
adapter->params.arch.nchan = NCHAN;
adapter->params.arch.vfcount = 128;
break;
case CHELSIO_T6:
adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
adapter->params.arch.sge_fl_db = 0;
adapter->params.arch.mps_tcam_size =
NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
adapter->params.arch.mps_rplc_size = 256;
adapter->params.arch.nchan = 2;
adapter->params.arch.vfcount = 256;
break;
default:
dev_err(adapter, "%s: Device %d is not supported\n",
__func__, adapter->params.pci.device_id);

15
drivers/net/cxgbe/base/t4_pci_id_tbl.h
View File

@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2014-2015 Chelsio Communications.
* Copyright(c) 2014-2017 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -144,6 +144,19 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
CH_PCI_ID_TABLE_FENTRY(0x5090), /* Custom T540-CR */
CH_PCI_ID_TABLE_FENTRY(0x5091), /* Custom T522-CR */
CH_PCI_ID_TABLE_FENTRY(0x5092), /* Custom T520-CR */
/* T6 adapter */
CH_PCI_ID_TABLE_FENTRY(0x6001), /* T6225-CR */
CH_PCI_ID_TABLE_FENTRY(0x6002), /* T6225-SO-CR */
CH_PCI_ID_TABLE_FENTRY(0x6003), /* T6425-CR */
CH_PCI_ID_TABLE_FENTRY(0x6005), /* T6225-OCP */
CH_PCI_ID_TABLE_FENTRY(0x6007), /* T62100-LP-CR */
CH_PCI_ID_TABLE_FENTRY(0x6008), /* T62100-SO-CR */
CH_PCI_ID_TABLE_FENTRY(0x600d), /* T62100-CR */
CH_PCI_ID_TABLE_FENTRY(0x6011), /* T6225-LL-CR */
CH_PCI_ID_TABLE_FENTRY(0x6014), /* T61100-OCP-SO */
CH_PCI_ID_TABLE_FENTRY(0x6080), /* Custom T6225-CR SFP28 */
CH_PCI_ID_TABLE_FENTRY(0x6081), /* Custom T62100-CR */
CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
#endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */

7
drivers/net/cxgbe/base/t4_regs.h
View File

@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2014-2015 Chelsio Communications.
* Copyright(c) 2014-2017 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -763,6 +763,11 @@
#define V_SOURCEPF(x) ((x) << S_SOURCEPF)
#define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
#define S_T6_SOURCEPF 9
#define M_T6_SOURCEPF 0x7U
#define V_T6_SOURCEPF(x) ((x) << S_T6_SOURCEPF)
#define G_T6_SOURCEPF(x) (((x) >> S_T6_SOURCEPF) & M_T6_SOURCEPF)
#define A_PL_PF_INT_ENABLE 0x3c4
#define S_PFSW 3

14
drivers/net/cxgbe/cxgbe_main.c
View File

@ -1,7 +1,7 @@
/*-
* BSD LICENSE
*
* Copyright(c) 2014-2016 Chelsio Communications.
* Copyright(c) 2014-2017 Chelsio Communications.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -1073,10 +1073,20 @@ void cxgbe_close(struct adapter *adapter)
int cxgbe_probe(struct adapter *adapter)
{
struct port_info *pi;
int chip;
int func, i;
int err = 0;
u32 whoami;
whoami = t4_read_reg(adapter, A_PL_WHOAMI);
chip = t4_get_chip_type(adapter,
CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
if (chip < 0)
return chip;
func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
func = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI));
adapter->mbox = func;
adapter->pf = func;