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net/ixgbe/base: add bit for enabling L3/L4 filtering

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Add a L3/L4 filtering definition of Multiple Receive Queues Command
(MRQC) register for the future use.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
This commit is contained in:
Wenzhuo Lu 2017-03-01 14:04:47 +08:00 committed by Ferruh Yigit
parent 90a02fce70
commit 04e395f20a
1 changed files with 1 additions and 0 deletions
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drivers/net/ixgbe/base/ixgbe_type.h
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@ -2622,6 +2622,7 @@ enum {
#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 /* Enable L3/L4 Tx switch */
#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000