eal/ppc: atomic operations for IBM Power
This patch adds architecture specific atomic operation file for IBM Power architecture CPU. Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com> Acked-by: David Marchand <david.marchand@6wind.com>
This commit is contained in:
Chao Zhu
Thomas Monjalon
parent
a982ec81d8
commit
05c3fd7110
426
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
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426
lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h
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/*
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* BSD LICENSE
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*
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* Copyright (C) IBM Corporation 2014.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of IBM Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Inspired from FreeBSD src/sys/powerpc/include/atomic.h
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* Copyright (c) 2008 Marcel Moolenaar
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* Copyright (c) 2001 Benno Rice
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* Copyright (c) 2001 David E. O'Brien
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*/
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#ifndef _RTE_ATOMIC_PPC_64_H_
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#define _RTE_ATOMIC_PPC_64_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "generic/rte_atomic.h"
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/**
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* General memory barrier.
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*
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* Guarantees that the LOAD and STORE operations generated before the
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* barrier occur before the LOAD and STORE operations generated after.
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*/
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#define rte_mb() {asm volatile("sync" : : : "memory"); }
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/**
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* Write memory barrier.
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*
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* Guarantees that the STORE operations generated before the barrier
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* occur before the STORE operations generated after.
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*/
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#define rte_wmb() {asm volatile("sync" : : : "memory"); }
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/**
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* Read memory barrier.
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*
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* Guarantees that the LOAD operations generated before the barrier
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* occur before the LOAD operations generated after.
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*/
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#define rte_rmb() {asm volatile("sync" : : : "memory"); }
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/*------------------------- 16 bit atomic operations -------------------------*/
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/* To be compatible with Power7, use GCC built-in functions for 16 bit
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* operations */
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#ifndef RTE_FORCE_INTRINSICS
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static inline int
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rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
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{
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return __atomic_compare_exchange(dst, &exp, &src, 0, __ATOMIC_ACQUIRE,
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__ATOMIC_ACQUIRE) ? 1 : 0;
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}
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static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
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{
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return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
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}
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static inline void
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rte_atomic16_inc(rte_atomic16_t *v)
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{
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__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
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}
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static inline void
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rte_atomic16_dec(rte_atomic16_t *v)
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{
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__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE);
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}
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static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
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{
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return (__atomic_add_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);
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}
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static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
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{
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return (__atomic_sub_fetch(&v->cnt, 1, __ATOMIC_ACQUIRE) == 0);
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}
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/*------------------------- 32 bit atomic operations -------------------------*/
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static inline int
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rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
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{
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unsigned int ret = 0;
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asm volatile(
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"\tlwsync\n"
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"1:\tlwarx %[ret], 0, %[dst]\n"
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"cmplw %[exp], %[ret]\n"
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"bne 2f\n"
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"stwcx. %[src], 0, %[dst]\n"
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"bne- 1b\n"
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"li %[ret], 1\n"
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"b 3f\n"
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"2:\n"
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"stwcx. %[ret], 0, %[dst]\n"
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"li %[ret], 0\n"
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"3:\n"
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"isync\n"
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: [ret] "=&r" (ret), "=m" (*dst)
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: [dst] "r" (dst),
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[exp] "r" (exp),
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[src] "r" (src),
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"m" (*dst)
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: "cc", "memory");
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return ret;
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}
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static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
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{
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return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
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}
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static inline void
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rte_atomic32_inc(rte_atomic32_t *v)
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{
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int t;
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asm volatile(
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"1: lwarx %[t],0,%[cnt]\n"
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"addic %[t],%[t],1\n"
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"stwcx. %[t],0,%[cnt]\n"
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"bne- 1b\n"
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: [t] "=&r" (t), "=m" (v->cnt)
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: [cnt] "r" (&v->cnt), "m" (v->cnt)
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: "cc", "xer", "memory");
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}
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static inline void
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rte_atomic32_dec(rte_atomic32_t *v)
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{
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int t;
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asm volatile(
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"1: lwarx %[t],0,%[cnt]\n"
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"addic %[t],%[t],-1\n"
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"stwcx. %[t],0,%[cnt]\n"
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"bne- 1b\n"
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: [t] "=&r" (t), "=m" (v->cnt)
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: [cnt] "r" (&v->cnt), "m" (v->cnt)
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: "cc", "xer", "memory");
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}
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static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
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{
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int ret;
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asm volatile(
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"\n\tlwsync\n"
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"1: lwarx %[ret],0,%[cnt]\n"
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"addic %[ret],%[ret],1\n"
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"stwcx. %[ret],0,%[cnt]\n"
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"bne- 1b\n"
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"isync\n"
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: [ret] "=&r" (ret)
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: [cnt] "r" (&v->cnt)
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: "cc", "xer", "memory");
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return (ret == 0);
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}
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static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
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{
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int ret;
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asm volatile(
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"\n\tlwsync\n"
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"1: lwarx %[ret],0,%[cnt]\n"
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"addic %[ret],%[ret],-1\n"
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"stwcx. %[ret],0,%[cnt]\n"
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"bne- 1b\n"
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"isync\n"
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: [ret] "=&r" (ret)
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: [cnt] "r" (&v->cnt)
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: "cc", "xer", "memory");
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return (ret == 0);
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}
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/*------------------------- 64 bit atomic operations -------------------------*/
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static inline int
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rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
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{
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unsigned int ret = 0;
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asm volatile (
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"\tlwsync\n"
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"1: ldarx %[ret], 0, %[dst]\n"
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"cmpld %[exp], %[ret]\n"
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"bne 2f\n"
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"stdcx. %[src], 0, %[dst]\n"
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"bne- 1b\n"
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"li %[ret], 1\n"
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"b 3f\n"
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"2:\n"
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"stdcx. %[ret], 0, %[dst]\n"
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"li %[ret], 0\n"
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"3:\n"
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"isync\n"
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: [ret] "=&r" (ret), "=m" (*dst)
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: [dst] "r" (dst),
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[exp] "r" (exp),
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[src] "r" (src),
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"m" (*dst)
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: "cc", "memory");
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return ret;
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}
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static inline void
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rte_atomic64_init(rte_atomic64_t *v)
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{
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v->cnt = 0;
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}
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static inline int64_t
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rte_atomic64_read(rte_atomic64_t *v)
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{
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long ret;
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asm volatile("ld%U1%X1 %[ret],%[cnt]"
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: [ret] "=r"(ret)
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: [cnt] "m"(v->cnt));
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return ret;
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}
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static inline void
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rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
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{
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asm volatile("std%U0%X0 %[new_value],%[cnt]"
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: [cnt] "=m"(v->cnt)
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: [new_value] "r"(new_value));
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}
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static inline void
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rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
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{
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long t;
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asm volatile(
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"1: ldarx %[t],0,%[cnt]\n"
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"add %[t],%[inc],%[t]\n"
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"stdcx. %[t],0,%[cnt]\n"
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"bne- 1b\n"
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: [t] "=&r" (t), "=m" (v->cnt)
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: [cnt] "r" (&v->cnt), [inc] "r" (inc), "m" (v->cnt)
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: "cc", "memory");
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}
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static inline void
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rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
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{
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long t;
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asm volatile(
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"1: ldarx %[t],0,%[cnt]\n"
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"subf %[t],%[dec],%[t]\n"
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"stdcx. %[t],0,%[cnt]\n"
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"bne- 1b\n"
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: [t] "=&r" (t), "+m" (v->cnt)
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: [cnt] "r" (&v->cnt), [dec] "r" (dec), "m" (v->cnt)
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: "cc", "memory");
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}
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static inline void
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rte_atomic64_inc(rte_atomic64_t *v)
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{
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long t;
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asm volatile(
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"1: ldarx %[t],0,%[cnt]\n"
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"addic %[t],%[t],1\n"
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"stdcx. %[t],0,%[cnt]\n"
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"bne- 1b\n"
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: [t] "=&r" (t), "+m" (v->cnt)
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: [cnt] "r" (&v->cnt), "m" (v->cnt)
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: "cc", "xer", "memory");
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}
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static inline void
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rte_atomic64_dec(rte_atomic64_t *v)
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{
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long t;
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asm volatile(
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"1: ldarx %[t],0,%[cnt]\n"
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"addic %[t],%[t],-1\n"
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"stdcx. %[t],0,%[cnt]\n"
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"bne- 1b\n"
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: [t] "=&r" (t), "+m" (v->cnt)
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: [cnt] "r" (&v->cnt), "m" (v->cnt)
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: "cc", "xer", "memory");
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}
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static inline int64_t
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rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
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{
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long ret;
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asm volatile(
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"\n\tlwsync\n"
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"1: ldarx %[ret],0,%[cnt]\n"
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"add %[ret],%[inc],%[ret]\n"
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"stdcx. %[ret],0,%[cnt]\n"
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"bne- 1b\n"
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"isync\n"
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: [ret] "=&r" (ret)
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: [inc] "r" (inc), [cnt] "r" (&v->cnt)
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: "cc", "memory");
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return ret;
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}
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static inline int64_t
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rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
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{
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long ret;
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asm volatile(
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"\n\tlwsync\n"
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"1: ldarx %[ret],0,%[cnt]\n"
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"subf %[ret],%[dec],%[ret]\n"
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"stdcx. %[ret],0,%[cnt]\n"
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"bne- 1b\n"
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"isync\n"
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: [ret] "=&r" (ret)
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: [dec] "r" (dec), [cnt] "r" (&v->cnt)
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: "cc", "memory");
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return ret;
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}
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static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
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{
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long ret;
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asm volatile(
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"\n\tlwsync\n"
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"1: ldarx %[ret],0,%[cnt]\n"
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"addic %[ret],%[ret],1\n"
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"stdcx. %[ret],0,%[cnt]\n"
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"bne- 1b\n"
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"isync\n"
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: [ret] "=&r" (ret)
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: [cnt] "r" (&v->cnt)
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: "cc", "xer", "memory");
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return (ret == 0);
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}
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static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
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{
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long ret;
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asm volatile(
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"\n\tlwsync\n"
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"1: ldarx %[ret],0,%[cnt]\n"
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"addic %[ret],%[ret],-1\n"
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"stdcx. %[ret],0,%[cnt]\n"
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"bne- 1b\n"
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"isync\n"
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: [ret] "=&r" (ret)
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: [cnt] "r" (&v->cnt)
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: "cc", "xer", "memory");
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return (ret == 0);
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}
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static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
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{
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return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
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}
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/**
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* Atomically set a 64-bit counter to 0.
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*
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* @param v
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* A pointer to the atomic counter.
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*/
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static inline void rte_atomic64_clear(rte_atomic64_t *v)
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{
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v->cnt = 0;
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTE_ATOMIC_PPC_64_H_ */
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