baseband/acc100: add queue configuration
Adding function to create and configure queues for the device. Still no capability. Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Reviewed-by: Rosen Xu <rosen.xu@intel.com> Acked-by: Liu Tianjiao <tianjiao.liu@intel.com> Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
This commit is contained in:
Nicolas Chautru
Akhil Goyal
parent
9200ffa5cd
commit
060e767293
@ -26,6 +26,22 @@ RTE_LOG_REGISTER(acc100_logtype, pmd.bb.acc100, DEBUG);
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RTE_LOG_REGISTER(acc100_logtype, pmd.bb.acc100, NOTICE);
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#endif
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/* Write to MMIO register address */
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static inline void
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mmio_write(void *addr, uint32_t value)
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{
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*((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
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}
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/* Write a register of a ACC100 device */
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static inline void
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acc100_reg_write(struct acc100_device *d, uint32_t offset, uint32_t payload)
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{
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void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset);
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mmio_write(reg_addr, payload);
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usleep(ACC100_LONG_WAIT);
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}
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/* Read a register of a ACC100 device */
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static inline uint32_t
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acc100_reg_read(struct acc100_device *d, uint32_t offset)
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@ -36,6 +52,22 @@ acc100_reg_read(struct acc100_device *d, uint32_t offset)
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return rte_le_to_cpu_32(ret);
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}
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/* Basic Implementation of Log2 for exact 2^N */
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static inline uint32_t
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log2_basic(uint32_t value)
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{
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return (value == 0) ? 0 : rte_bsf32(value);
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}
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/* Calculate memory alignment offset assuming alignment is 2^N */
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static inline uint32_t
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calc_mem_alignment_offset(void *unaligned_virt_mem, uint32_t alignment)
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{
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rte_iova_t unaligned_phy_mem = rte_malloc_virt2iova(unaligned_virt_mem);
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return (uint32_t)(alignment -
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(unaligned_phy_mem & (alignment-1)));
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}
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/* Calculate the offset of the enqueue register */
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static inline uint32_t
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queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)
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@ -208,10 +240,416 @@ fetch_acc100_config(struct rte_bbdev *dev)
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acc100_conf->q_dl_5g.aq_depth_log2);
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}
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/* Free 64MB memory used for software rings */
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static int
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acc100_dev_close(struct rte_bbdev *dev __rte_unused)
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static void
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free_base_addresses(void **base_addrs, int size)
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{
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int i;
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for (i = 0; i < size; i++)
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rte_free(base_addrs[i]);
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}
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static inline uint32_t
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get_desc_len(void)
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{
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return sizeof(union acc100_dma_desc);
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}
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/* Allocate the 2 * 64MB block for the sw rings */
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static int
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alloc_2x64mb_sw_rings_mem(struct rte_bbdev *dev, struct acc100_device *d,
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int socket)
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{
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uint32_t sw_ring_size = ACC100_SIZE_64MBYTE;
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d->sw_rings_base = rte_zmalloc_socket(dev->device->driver->name,
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2 * sw_ring_size, RTE_CACHE_LINE_SIZE, socket);
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if (d->sw_rings_base == NULL) {
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rte_bbdev_log(ERR, "Failed to allocate memory for %s:%u",
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dev->device->driver->name,
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dev->data->dev_id);
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return -ENOMEM;
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}
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uint32_t next_64mb_align_offset = calc_mem_alignment_offset(
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d->sw_rings_base, ACC100_SIZE_64MBYTE);
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d->sw_rings = RTE_PTR_ADD(d->sw_rings_base, next_64mb_align_offset);
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d->sw_rings_iova = rte_malloc_virt2iova(d->sw_rings_base) +
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next_64mb_align_offset;
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d->sw_ring_size = ACC100_MAX_QUEUE_DEPTH * get_desc_len();
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d->sw_ring_max_depth = ACC100_MAX_QUEUE_DEPTH;
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return 0;
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}
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/* Attempt to allocate minimised memory space for sw rings */
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static void
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alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc100_device *d,
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uint16_t num_queues, int socket)
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{
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rte_iova_t sw_rings_base_iova, next_64mb_align_addr_iova;
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uint32_t next_64mb_align_offset;
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rte_iova_t sw_ring_iova_end_addr;
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void *base_addrs[ACC100_SW_RING_MEM_ALLOC_ATTEMPTS];
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void *sw_rings_base;
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int i = 0;
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uint32_t q_sw_ring_size = ACC100_MAX_QUEUE_DEPTH * get_desc_len();
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uint32_t dev_sw_ring_size = q_sw_ring_size * num_queues;
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/* Find an aligned block of memory to store sw rings */
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while (i < ACC100_SW_RING_MEM_ALLOC_ATTEMPTS) {
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/*
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* sw_ring allocated memory is guaranteed to be aligned to
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* q_sw_ring_size at the condition that the requested size is
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* less than the page size
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*/
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sw_rings_base = rte_zmalloc_socket(
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dev->device->driver->name,
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dev_sw_ring_size, q_sw_ring_size, socket);
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if (sw_rings_base == NULL) {
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rte_bbdev_log(ERR,
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"Failed to allocate memory for %s:%u",
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dev->device->driver->name,
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dev->data->dev_id);
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break;
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}
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sw_rings_base_iova = rte_malloc_virt2iova(sw_rings_base);
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next_64mb_align_offset = calc_mem_alignment_offset(
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sw_rings_base, ACC100_SIZE_64MBYTE);
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next_64mb_align_addr_iova = sw_rings_base_iova +
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next_64mb_align_offset;
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sw_ring_iova_end_addr = sw_rings_base_iova + dev_sw_ring_size;
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/* Check if the end of the sw ring memory block is before the
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* start of next 64MB aligned mem address
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*/
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if (sw_ring_iova_end_addr < next_64mb_align_addr_iova) {
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d->sw_rings_iova = sw_rings_base_iova;
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d->sw_rings = sw_rings_base;
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d->sw_rings_base = sw_rings_base;
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d->sw_ring_size = q_sw_ring_size;
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d->sw_ring_max_depth = ACC100_MAX_QUEUE_DEPTH;
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break;
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}
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/* Store the address of the unaligned mem block */
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base_addrs[i] = sw_rings_base;
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i++;
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}
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/* Free all unaligned blocks of mem allocated in the loop */
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free_base_addresses(base_addrs, i);
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}
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/* Allocate 64MB memory used for all software rings */
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static int
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acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
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{
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uint32_t phys_low, phys_high, payload;
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struct acc100_device *d = dev->data->dev_private;
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const struct acc100_registry_addr *reg_addr;
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if (d->pf_device && !d->acc100_conf.pf_mode_en) {
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rte_bbdev_log(NOTICE,
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"%s has PF mode disabled. This PF can't be used.",
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dev->data->name);
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return -ENODEV;
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}
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alloc_sw_rings_min_mem(dev, d, num_queues, socket_id);
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/* If minimal memory space approach failed, then allocate
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* the 2 * 64MB block for the sw rings
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*/
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if (d->sw_rings == NULL)
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alloc_2x64mb_sw_rings_mem(dev, d, socket_id);
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if (d->sw_rings == NULL) {
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rte_bbdev_log(NOTICE,
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"Failure allocating sw_rings memory");
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return -ENODEV;
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}
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/* Configure ACC100 with the base address for DMA descriptor rings
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* Same descriptor rings used for UL and DL DMA Engines
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* Note : Assuming only VF0 bundle is used for PF mode
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*/
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phys_high = (uint32_t)(d->sw_rings_iova >> 32);
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phys_low = (uint32_t)(d->sw_rings_iova & ~(ACC100_SIZE_64MBYTE-1));
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/* Choose correct registry addresses for the device type */
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if (d->pf_device)
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reg_addr = &pf_reg_addr;
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else
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reg_addr = &vf_reg_addr;
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/* Read the populated cfg from ACC100 registers */
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fetch_acc100_config(dev);
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/* Release AXI from PF */
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if (d->pf_device)
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acc100_reg_write(d, HWPfDmaAxiControl, 1);
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acc100_reg_write(d, reg_addr->dma_ring_ul5g_hi, phys_high);
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acc100_reg_write(d, reg_addr->dma_ring_ul5g_lo, phys_low);
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acc100_reg_write(d, reg_addr->dma_ring_dl5g_hi, phys_high);
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acc100_reg_write(d, reg_addr->dma_ring_dl5g_lo, phys_low);
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acc100_reg_write(d, reg_addr->dma_ring_ul4g_hi, phys_high);
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acc100_reg_write(d, reg_addr->dma_ring_ul4g_lo, phys_low);
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acc100_reg_write(d, reg_addr->dma_ring_dl4g_hi, phys_high);
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acc100_reg_write(d, reg_addr->dma_ring_dl4g_lo, phys_low);
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/*
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* Configure Ring Size to the max queue ring size
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* (used for wrapping purpose)
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*/
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payload = log2_basic(d->sw_ring_size / 64);
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acc100_reg_write(d, reg_addr->ring_size, payload);
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/* Configure tail pointer for use when SDONE enabled */
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d->tail_ptrs = rte_zmalloc_socket(
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dev->device->driver->name,
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ACC100_NUM_QGRPS * ACC100_NUM_AQS * sizeof(uint32_t),
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RTE_CACHE_LINE_SIZE, socket_id);
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if (d->tail_ptrs == NULL) {
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rte_bbdev_log(ERR, "Failed to allocate tail ptr for %s:%u",
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dev->device->driver->name,
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dev->data->dev_id);
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rte_free(d->sw_rings);
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return -ENOMEM;
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}
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d->tail_ptr_iova = rte_malloc_virt2iova(d->tail_ptrs);
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phys_high = (uint32_t)(d->tail_ptr_iova >> 32);
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phys_low = (uint32_t)(d->tail_ptr_iova);
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acc100_reg_write(d, reg_addr->tail_ptrs_ul5g_hi, phys_high);
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acc100_reg_write(d, reg_addr->tail_ptrs_ul5g_lo, phys_low);
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acc100_reg_write(d, reg_addr->tail_ptrs_dl5g_hi, phys_high);
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acc100_reg_write(d, reg_addr->tail_ptrs_dl5g_lo, phys_low);
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acc100_reg_write(d, reg_addr->tail_ptrs_ul4g_hi, phys_high);
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acc100_reg_write(d, reg_addr->tail_ptrs_ul4g_lo, phys_low);
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acc100_reg_write(d, reg_addr->tail_ptrs_dl4g_hi, phys_high);
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acc100_reg_write(d, reg_addr->tail_ptrs_dl4g_lo, phys_low);
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d->harq_layout = rte_zmalloc_socket("HARQ Layout",
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ACC100_HARQ_LAYOUT * sizeof(*d->harq_layout),
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RTE_CACHE_LINE_SIZE, dev->data->socket_id);
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if (d->harq_layout == NULL) {
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rte_bbdev_log(ERR, "Failed to allocate harq_layout for %s:%u",
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dev->device->driver->name,
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dev->data->dev_id);
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rte_free(d->sw_rings);
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return -ENOMEM;
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}
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/* Mark as configured properly */
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d->configured = true;
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rte_bbdev_log_debug(
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"ACC100 (%s) configured sw_rings = %p, sw_rings_iova = %#"
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PRIx64, dev->data->name, d->sw_rings, d->sw_rings_iova);
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return 0;
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}
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/* Free memory used for software rings */
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static int
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acc100_dev_close(struct rte_bbdev *dev)
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{
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struct acc100_device *d = dev->data->dev_private;
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if (d->sw_rings_base != NULL) {
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rte_free(d->tail_ptrs);
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rte_free(d->sw_rings_base);
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d->sw_rings_base = NULL;
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}
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/* Ensure all in flight HW transactions are completed */
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usleep(ACC100_LONG_WAIT);
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return 0;
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}
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/**
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* Report a ACC100 queue index which is free
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* Return 0 to 16k for a valid queue_idx or -1 when no queue is available
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* Note : Only supporting VF0 Bundle for PF mode
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*/
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static int
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acc100_find_free_queue_idx(struct rte_bbdev *dev,
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const struct rte_bbdev_queue_conf *conf)
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{
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struct acc100_device *d = dev->data->dev_private;
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int op_2_acc[5] = {0, UL_4G, DL_4G, UL_5G, DL_5G};
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int acc = op_2_acc[conf->op_type];
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struct rte_acc100_queue_topology *qtop = NULL;
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qtopFromAcc(&qtop, acc, &(d->acc100_conf));
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if (qtop == NULL)
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return -1;
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/* Identify matching QGroup Index which are sorted in priority order */
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uint16_t group_idx = qtop->first_qgroup_index;
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group_idx += conf->priority;
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if (group_idx >= ACC100_NUM_QGRPS ||
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conf->priority >= qtop->num_qgroups) {
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rte_bbdev_log(INFO, "Invalid Priority on %s, priority %u",
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dev->data->name, conf->priority);
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return -1;
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}
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/* Find a free AQ_idx */
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uint16_t aq_idx;
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for (aq_idx = 0; aq_idx < qtop->num_aqs_per_groups; aq_idx++) {
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if (((d->q_assigned_bit_map[group_idx] >> aq_idx) & 0x1) == 0) {
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/* Mark the Queue as assigned */
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d->q_assigned_bit_map[group_idx] |= (1 << aq_idx);
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/* Report the AQ Index */
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return (group_idx << ACC100_GRP_ID_SHIFT) + aq_idx;
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}
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}
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rte_bbdev_log(INFO, "Failed to find free queue on %s, priority %u",
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dev->data->name, conf->priority);
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return -1;
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}
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/* Setup ACC100 queue */
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static int
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acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
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const struct rte_bbdev_queue_conf *conf)
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{
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struct acc100_device *d = dev->data->dev_private;
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struct acc100_queue *q;
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int16_t q_idx;
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/* Allocate the queue data structure. */
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q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),
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RTE_CACHE_LINE_SIZE, conf->socket);
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if (q == NULL) {
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rte_bbdev_log(ERR, "Failed to allocate queue memory");
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return -ENOMEM;
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}
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if (d == NULL) {
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rte_bbdev_log(ERR, "Undefined device");
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return -ENODEV;
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}
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q->d = d;
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q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));
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q->ring_addr_iova = d->sw_rings_iova + (d->sw_ring_size * queue_id);
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/* Prepare the Ring with default descriptor format */
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union acc100_dma_desc *desc = NULL;
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unsigned int desc_idx, b_idx;
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int fcw_len = (conf->op_type == RTE_BBDEV_OP_LDPC_ENC ?
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ACC100_FCW_LE_BLEN : (conf->op_type == RTE_BBDEV_OP_TURBO_DEC ?
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ACC100_FCW_TD_BLEN : ACC100_FCW_LD_BLEN));
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for (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) {
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desc = q->ring_addr + desc_idx;
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desc->req.word0 = ACC100_DMA_DESC_TYPE;
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desc->req.word1 = 0; /**< Timestamp */
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desc->req.word2 = 0;
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desc->req.word3 = 0;
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uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
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desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset;
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desc->req.data_ptrs[0].blen = fcw_len;
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desc->req.data_ptrs[0].blkid = ACC100_DMA_BLKID_FCW;
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desc->req.data_ptrs[0].last = 0;
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desc->req.data_ptrs[0].dma_ext = 0;
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for (b_idx = 1; b_idx < ACC100_DMA_MAX_NUM_POINTERS - 1;
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b_idx++) {
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desc->req.data_ptrs[b_idx].blkid = ACC100_DMA_BLKID_IN;
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desc->req.data_ptrs[b_idx].last = 1;
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desc->req.data_ptrs[b_idx].dma_ext = 0;
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b_idx++;
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desc->req.data_ptrs[b_idx].blkid =
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ACC100_DMA_BLKID_OUT_ENC;
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desc->req.data_ptrs[b_idx].last = 1;
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desc->req.data_ptrs[b_idx].dma_ext = 0;
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}
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/* Preset some fields of LDPC FCW */
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desc->req.fcw_ld.FCWversion = ACC100_FCW_VER;
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desc->req.fcw_ld.gain_i = 1;
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desc->req.fcw_ld.gain_h = 1;
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}
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q->lb_in = rte_zmalloc_socket(dev->device->driver->name,
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RTE_CACHE_LINE_SIZE,
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RTE_CACHE_LINE_SIZE, conf->socket);
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if (q->lb_in == NULL) {
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rte_bbdev_log(ERR, "Failed to allocate lb_in memory");
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rte_free(q);
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return -ENOMEM;
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}
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q->lb_in_addr_iova = rte_malloc_virt2iova(q->lb_in);
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q->lb_out = rte_zmalloc_socket(dev->device->driver->name,
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RTE_CACHE_LINE_SIZE,
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RTE_CACHE_LINE_SIZE, conf->socket);
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if (q->lb_out == NULL) {
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rte_bbdev_log(ERR, "Failed to allocate lb_out memory");
|
||||
rte_free(q->lb_in);
|
||||
rte_free(q);
|
||||
return -ENOMEM;
|
||||
}
|
||||
q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out);
|
||||
|
||||
/*
|
||||
* Software queue ring wraps synchronously with the HW when it reaches
|
||||
* the boundary of the maximum allocated queue size, no matter what the
|
||||
* sw queue size is. This wrapping is guarded by setting the wrap_mask
|
||||
* to represent the maximum queue size as allocated at the time when
|
||||
* the device has been setup (in configure()).
|
||||
*
|
||||
* The queue depth is set to the queue size value (conf->queue_size).
|
||||
* This limits the occupancy of the queue at any point of time, so that
|
||||
* the queue does not get swamped with enqueue requests.
|
||||
*/
|
||||
q->sw_ring_depth = conf->queue_size;
|
||||
q->sw_ring_wrap_mask = d->sw_ring_max_depth - 1;
|
||||
|
||||
q->op_type = conf->op_type;
|
||||
|
||||
q_idx = acc100_find_free_queue_idx(dev, conf);
|
||||
if (q_idx == -1) {
|
||||
rte_free(q->lb_in);
|
||||
rte_free(q->lb_out);
|
||||
rte_free(q);
|
||||
return -1;
|
||||
}
|
||||
|
||||
q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF;
|
||||
q->vf_id = (q_idx >> ACC100_VF_ID_SHIFT) & 0x3F;
|
||||
q->aq_id = q_idx & 0xF;
|
||||
q->aq_depth = (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) ?
|
||||
(1 << d->acc100_conf.q_ul_4g.aq_depth_log2) :
|
||||
(1 << d->acc100_conf.q_dl_4g.aq_depth_log2);
|
||||
|
||||
q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base,
|
||||
queue_offset(d->pf_device,
|
||||
q->vf_id, q->qgrp_id, q->aq_id));
|
||||
|
||||
rte_bbdev_log_debug(
|
||||
"Setup dev%u q%u: qgrp_id=%u, vf_id=%u, aq_id=%u, aq_depth=%u, mmio_reg_enqueue=%p",
|
||||
dev->data->dev_id, queue_id, q->qgrp_id, q->vf_id,
|
||||
q->aq_id, q->aq_depth, q->mmio_reg_enqueue);
|
||||
|
||||
dev->data->queues[queue_id].queue_private = q;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Release ACC100 queue */
|
||||
static int
|
||||
acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id)
|
||||
{
|
||||
struct acc100_device *d = dev->data->dev_private;
|
||||
struct acc100_queue *q = dev->data->queues[q_id].queue_private;
|
||||
|
||||
if (q != NULL) {
|
||||
/* Mark the Queue as un-assigned */
|
||||
d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFF -
|
||||
(1 << q->aq_id));
|
||||
rte_free(q->lb_in);
|
||||
rte_free(q->lb_out);
|
||||
rte_free(q);
|
||||
dev->data->queues[q_id].queue_private = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -262,8 +700,11 @@ acc100_dev_info_get(struct rte_bbdev *dev,
|
||||
}
|
||||
|
||||
static const struct rte_bbdev_ops acc100_bbdev_ops = {
|
||||
.setup_queues = acc100_setup_queues,
|
||||
.close = acc100_dev_close,
|
||||
.info_get = acc100_dev_info_get,
|
||||
.queue_setup = acc100_queue_setup,
|
||||
.queue_release = acc100_queue_release,
|
||||
};
|
||||
|
||||
/* ACC100 PCI PF address map */
|
||||
|
||||
@ -522,11 +522,56 @@ static const struct acc100_registry_addr vf_reg_addr = {
|
||||
.ddr_range = HWVfDmaDdrBaseRangeRoVf,
|
||||
};
|
||||
|
||||
/* Structure associated with each queue. */
|
||||
struct __rte_cache_aligned acc100_queue {
|
||||
union acc100_dma_desc *ring_addr; /* Virtual address of sw ring */
|
||||
rte_iova_t ring_addr_iova; /* IOVA address of software ring */
|
||||
uint32_t sw_ring_head; /* software ring head */
|
||||
uint32_t sw_ring_tail; /* software ring tail */
|
||||
/* software ring size (descriptors, not bytes) */
|
||||
uint32_t sw_ring_depth;
|
||||
/* mask used to wrap enqueued descriptors on the sw ring */
|
||||
uint32_t sw_ring_wrap_mask;
|
||||
/* MMIO register used to enqueue descriptors */
|
||||
void *mmio_reg_enqueue;
|
||||
uint8_t vf_id; /* VF ID (max = 63) */
|
||||
uint8_t qgrp_id; /* Queue Group ID */
|
||||
uint16_t aq_id; /* Atomic Queue ID */
|
||||
uint16_t aq_depth; /* Depth of atomic queue */
|
||||
uint32_t aq_enqueued; /* Count how many "batches" have been enqueued */
|
||||
uint32_t aq_dequeued; /* Count how many "batches" have been dequeued */
|
||||
uint32_t irq_enable; /* Enable ops dequeue interrupts if set to 1 */
|
||||
struct rte_mempool *fcw_mempool; /* FCW mempool */
|
||||
enum rte_bbdev_op_type op_type; /* Type of this Queue: TE or TD */
|
||||
/* Internal Buffers for loopback input */
|
||||
uint8_t *lb_in;
|
||||
uint8_t *lb_out;
|
||||
rte_iova_t lb_in_addr_iova;
|
||||
rte_iova_t lb_out_addr_iova;
|
||||
struct acc100_device *d;
|
||||
};
|
||||
|
||||
/* Private data structure for each ACC100 device */
|
||||
struct acc100_device {
|
||||
void *mmio_base; /**< Base address of MMIO registers (BAR0) */
|
||||
void *sw_rings_base; /* Base addr of un-aligned memory for sw rings */
|
||||
void *sw_rings; /* 64MBs of 64MB aligned memory for sw rings */
|
||||
rte_iova_t sw_rings_iova; /* IOVA address of sw_rings */
|
||||
/* Virtual address of the info memory routed to the this function under
|
||||
* operation, whether it is PF or VF.
|
||||
*/
|
||||
union acc100_harq_layout_data *harq_layout;
|
||||
uint32_t sw_ring_size;
|
||||
uint32_t ddr_size; /* Size in kB */
|
||||
uint32_t *tail_ptrs; /* Base address of response tail pointer buffer */
|
||||
rte_iova_t tail_ptr_iova; /* IOVA address of tail pointers */
|
||||
/* Max number of entries available for each queue in device, depending
|
||||
* on how many queues are enabled with configure()
|
||||
*/
|
||||
uint32_t sw_ring_max_depth;
|
||||
struct rte_acc100_conf acc100_conf; /* ACC100 Initial configuration */
|
||||
/* Bitmap capturing which Queues have already been assigned */
|
||||
uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
|
||||
bool pf_device; /**< True if this is a PF ACC100 device */
|
||||
bool configured; /**< True if this ACC100 device is configured */
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user