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examples/qos_sched: support PIE congestion management

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patch add support enable PIE or RED by
parsing config file.

Signed-off-by: Wojciech Liguzinski <wojciechx.liguzinski@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Acked-by: Jasvinder Singh <jasvinder.singh@intel.com>
This commit is contained in:
Wojciech Liguzinski 2021-11-04 11:03:34 +00:00 committed by Thomas Monjalon
parent 44c730b0e3
commit 06135957c4
5 changed files with 233 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

121
examples/qos_sched/cfg_file.c
View File

@ -229,6 +229,40 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg,
return 0;
}
#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p)
{
int j, k;
subport_p->cman_params->cman_mode = cman_p.cman_mode;
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
if (subport_p->cman_params->cman_mode ==
RTE_SCHED_CMAN_RED) {
for (k = 0; k < RTE_COLORS; k++) {
subport_p->cman_params->red_params[j][k].min_th =
cman_p.red_params[j][k].min_th;
subport_p->cman_params->red_params[j][k].max_th =
cman_p.red_params[j][k].max_th;
subport_p->cman_params->red_params[j][k].maxp_inv =
cman_p.red_params[j][k].maxp_inv;
subport_p->cman_params->red_params[j][k].wq_log2 =
cman_p.red_params[j][k].wq_log2;
}
} else {
subport_p->cman_params->pie_params[j].qdelay_ref =
cman_p.pie_params[j].qdelay_ref;
subport_p->cman_params->pie_params[j].dp_update_interval =
cman_p.pie_params[j].dp_update_interval;
subport_p->cman_params->pie_params[j].max_burst =
cman_p.pie_params[j].max_burst;
subport_p->cman_params->pie_params[j].tailq_th =
cman_p.pie_params[j].tailq_th;
}
}
}
#endif
int
cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params)
{
@ -243,24 +277,25 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
n_active_queues = 0;
#ifdef RTE_SCHED_CMAN
char sec_name[CFG_NAME_LEN];
struct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = { },
};
snprintf(sec_name, sizeof(sec_name), "red");
if (rte_cfgfile_has_section(cfg, sec_name)) {
if (rte_cfgfile_has_section(cfg, "red")) {
cman_params.cman_mode = RTE_SCHED_CMAN_RED;
for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
char str[32];
/* Parse WRED min thresholds */
snprintf(str, sizeof(str), "tc %d wred min", i);
entry = rte_cfgfile_get_entry(cfg, sec_name, str);
/* Parse RED min thresholds */
snprintf(str, sizeof(str), "tc %d red min", i);
entry = rte_cfgfile_get_entry(cfg, "red", str);
if (entry) {
char *next;
/* for each packet colour (green, yellow, red) */
for (j = 0; j < RTE_COLORS; j++) {
red_params[i][j].min_th
cman_params.red_params[i][j].min_th
= (uint16_t)strtol(entry, &next, 10);
if (next == NULL)
break;
@ -268,14 +303,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
/* Parse WRED max thresholds */
snprintf(str, sizeof(str), "tc %d wred max", i);
/* Parse RED max thresholds */
snprintf(str, sizeof(str), "tc %d red max", i);
entry = rte_cfgfile_get_entry(cfg, "red", str);
if (entry) {
char *next;
/* for each packet colour (green, yellow, red) */
for (j = 0; j < RTE_COLORS; j++) {
red_params[i][j].max_th
cman_params.red_params[i][j].max_th
= (uint16_t)strtol(entry, &next, 10);
if (next == NULL)
break;
@ -283,14 +318,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
/* Parse WRED inverse mark probabilities */
snprintf(str, sizeof(str), "tc %d wred inv prob", i);
/* Parse RED inverse mark probabilities */
snprintf(str, sizeof(str), "tc %d red inv prob", i);
entry = rte_cfgfile_get_entry(cfg, "red", str);
if (entry) {
char *next;
/* for each packet colour (green, yellow, red) */
for (j = 0; j < RTE_COLORS; j++) {
red_params[i][j].maxp_inv
cman_params.red_params[i][j].maxp_inv
= (uint8_t)strtol(entry, &next, 10);
if (next == NULL)
@ -299,14 +334,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
/* Parse WRED EWMA filter weights */
snprintf(str, sizeof(str), "tc %d wred weight", i);
/* Parse RED EWMA filter weights */
snprintf(str, sizeof(str), "tc %d red weight", i);
entry = rte_cfgfile_get_entry(cfg, "red", str);
if (entry) {
char *next;
/* for each packet colour (green, yellow, red) */
for (j = 0; j < RTE_COLORS; j++) {
red_params[i][j].wq_log2
cman_params.red_params[i][j].wq_log2
= (uint8_t)strtol(entry, &next, 10);
if (next == NULL)
break;
@ -315,6 +350,43 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
}
if (rte_cfgfile_has_section(cfg, "pie")) {
cman_params.cman_mode = RTE_SCHED_CMAN_PIE;
for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {
char str[32];
/* Parse Queue Delay Ref value */
snprintf(str, sizeof(str), "tc %d qdelay ref", i);
entry = rte_cfgfile_get_entry(cfg, "pie", str);
if (entry)
cman_params.pie_params[i].qdelay_ref =
(uint16_t) atoi(entry);
/* Parse Max Burst value */
snprintf(str, sizeof(str), "tc %d max burst", i);
entry = rte_cfgfile_get_entry(cfg, "pie", str);
if (entry)
cman_params.pie_params[i].max_burst =
(uint16_t) atoi(entry);
/* Parse Update Interval Value */
snprintf(str, sizeof(str), "tc %d update interval", i);
entry = rte_cfgfile_get_entry(cfg, "pie", str);
if (entry)
cman_params.pie_params[i].dp_update_interval =
(uint16_t) atoi(entry);
/* Parse Tailq Threshold Value */
snprintf(str, sizeof(str), "tc %d tailq th", i);
entry = rte_cfgfile_get_entry(cfg, "pie", str);
if (entry)
cman_params.pie_params[i].tailq_th =
(uint16_t) atoi(entry);
}
}
#endif /* RTE_SCHED_CMAN */
for (i = 0; i < MAX_SCHED_SUBPORTS; i++) {
@ -394,18 +466,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo
}
}
#ifdef RTE_SCHED_CMAN
for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) {
for (k = 0; k < RTE_COLORS; k++) {
subport_params[i].red_params[j][k].min_th =
red_params[j][k].min_th;
subport_params[i].red_params[j][k].max_th =
red_params[j][k].max_th;
subport_params[i].red_params[j][k].maxp_inv =
red_params[j][k].maxp_inv;
subport_params[i].red_params[j][k].wq_log2 =
red_params[j][k].wq_log2;
}
}
set_subport_cman_params(subport_params+i, cman_params);
#endif
}
}

5
examples/qos_sched/cfg_file.h
View File

@ -12,6 +12,11 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port);
int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe);
#ifdef RTE_SCHED_CMAN
void set_subport_cman_params(struct rte_sched_subport_params *subport_p,
struct rte_sched_cman_params cman_p);
#endif
int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport);
int cfg_load_subport_profile(struct rte_cfgfile *cfg,

23
examples/qos_sched/init.c
View File

@ -203,15 +203,9 @@ static struct rte_sched_subport_profile_params
},
};
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
.n_pipes_per_subport_enabled = 4096,
.qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
.pipe_profiles = pipe_profiles,
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
#ifdef RTE_SCHED_CMAN
struct rte_sched_cman_params cman_params = {
.cman_mode = RTE_SCHED_CMAN_RED,
.red_params = {
/* Traffic Class 0 Colors Green / Yellow / Red */
[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
@ -278,6 +272,19 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
[12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
};
#endif /* RTE_SCHED_CMAN */
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
.n_pipes_per_subport_enabled = 4096,
.qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
.pipe_profiles = pipe_profiles,
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
#ifdef RTE_SCHED_CMAN
.cman_params = &cman_params,
#endif /* RTE_SCHED_CMAN */
},
};

3
examples/qos_sched/main.h
View File

@ -153,6 +153,9 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE];
extern uint32_t n_active_queues;
extern struct rte_sched_port_params port_params;
#ifdef RTE_SCHED_CMAN
extern struct rte_sched_cman_params cman_params;
#endif
extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS];
int app_parse_args(int argc, char **argv);

172
examples/qos_sched/profile.cfg
View File

@ -76,68 +76,134 @@ tc 12 oversubscription weight = 1
tc 12 wrr weights = 1 1 1 1
; RED params per traffic class and color (Green / Yellow / Red)
[red]
tc 0 wred min = 48 40 32
tc 0 wred max = 64 64 64
tc 0 wred inv prob = 10 10 10
tc 0 wred weight = 9 9 9
;[red]
;tc 0 wred min = 48 40 32
;tc 0 wred max = 64 64 64
;tc 0 wred inv prob = 10 10 10
;tc 0 wred weight = 9 9 9
tc 1 wred min = 48 40 32
tc 1 wred max = 64 64 64
tc 1 wred inv prob = 10 10 10
tc 1 wred weight = 9 9 9
;tc 1 wred min = 48 40 32
;tc 1 wred max = 64 64 64
;tc 1 wred inv prob = 10 10 10
;tc 1 wred weight = 9 9 9
tc 2 wred min = 48 40 32
tc 2 wred max = 64 64 64
tc 2 wred inv prob = 10 10 10
tc 2 wred weight = 9 9 9
;tc 2 wred min = 48 40 32
;tc 2 wred max = 64 64 64
;tc 2 wred inv prob = 10 10 10
;tc 2 wred weight = 9 9 9
tc 3 wred min = 48 40 32
tc 3 wred max = 64 64 64
tc 3 wred inv prob = 10 10 10
tc 3 wred weight = 9 9 9
;tc 3 wred min = 48 40 32
;tc 3 wred max = 64 64 64
;tc 3 wred inv prob = 10 10 10
;tc 3 wred weight = 9 9 9
tc 4 wred min = 48 40 32
tc 4 wred max = 64 64 64
tc 4 wred inv prob = 10 10 10
tc 4 wred weight = 9 9 9
;tc 4 wred min = 48 40 32
;tc 4 wred max = 64 64 64
;tc 4 wred inv prob = 10 10 10
;tc 4 wred weight = 9 9 9
tc 5 wred min = 48 40 32
tc 5 wred max = 64 64 64
tc 5 wred inv prob = 10 10 10
tc 5 wred weight = 9 9 9
;tc 5 wred min = 48 40 32
;tc 5 wred max = 64 64 64
;tc 5 wred inv prob = 10 10 10
;tc 5 wred weight = 9 9 9
tc 6 wred min = 48 40 32
tc 6 wred max = 64 64 64
tc 6 wred inv prob = 10 10 10
tc 6 wred weight = 9 9 9
;tc 6 wred min = 48 40 32
;tc 6 wred max = 64 64 64
;tc 6 wred inv prob = 10 10 10
;tc 6 wred weight = 9 9 9
tc 7 wred min = 48 40 32
tc 7 wred max = 64 64 64
tc 7 wred inv prob = 10 10 10
tc 7 wred weight = 9 9 9
;tc 7 wred min = 48 40 32
;tc 7 wred max = 64 64 64
;tc 7 wred inv prob = 10 10 10
;tc 7 wred weight = 9 9 9
tc 8 wred min = 48 40 32
tc 8 wred max = 64 64 64
tc 8 wred inv prob = 10 10 10
tc 8 wred weight = 9 9 9
;tc 8 wred min = 48 40 32
;tc 8 wred max = 64 64 64
;tc 8 wred inv prob = 10 10 10
;tc 8 wred weight = 9 9 9
tc 9 wred min = 48 40 32
tc 9 wred max = 64 64 64
tc 9 wred inv prob = 10 10 10
tc 9 wred weight = 9 9 9
;tc 9 wred min = 48 40 32
;tc 9 wred max = 64 64 64
;tc 9 wred inv prob = 10 10 10
;tc 9 wred weight = 9 9 9
tc 10 wred min = 48 40 32
tc 10 wred max = 64 64 64
tc 10 wred inv prob = 10 10 10
tc 10 wred weight = 9 9 9
;tc 10 wred min = 48 40 32
;tc 10 wred max = 64 64 64
;tc 10 wred inv prob = 10 10 10
;tc 10 wred weight = 9 9 9
tc 11 wred min = 48 40 32
tc 11 wred max = 64 64 64
tc 11 wred inv prob = 10 10 10
tc 11 wred weight = 9 9 9
;tc 11 wred min = 48 40 32
;tc 11 wred max = 64 64 64
;tc 11 wred inv prob = 10 10 10
;tc 11 wred weight = 9 9 9
tc 12 wred min = 48 40 32
tc 12 wred max = 64 64 64
tc 12 wred inv prob = 10 10 10
tc 12 wred weight = 9 9 9
;tc 12 wred min = 48 40 32
;tc 12 wred max = 64 64 64
;tc 12 wred inv prob = 10 10 10
;tc 12 wred weight = 9 9 9
[pie]
tc 0 qdelay ref = 15
tc 0 max burst = 150
tc 0 update interval = 15
tc 0 tailq th = 64
tc 1 qdelay ref = 15
tc 1 max burst = 150
tc 1 update interval = 15
tc 1 tailq th = 64
tc 2 qdelay ref = 15
tc 2 max burst = 150
tc 2 update interval = 15
tc 2 tailq th = 64
tc 3 qdelay ref = 15
tc 3 max burst = 150
tc 3 update interval = 15
tc 3 tailq th = 64
tc 4 qdelay ref = 15
tc 4 max burst = 150
tc 4 update interval = 15
tc 4 tailq th = 64
tc 5 qdelay ref = 15
tc 5 max burst = 150
tc 5 update interval = 15
tc 5 tailq th = 64
tc 6 qdelay ref = 15
tc 6 max burst = 150
tc 6 update interval = 15
tc 6 tailq th = 64
tc 7 qdelay ref = 15
tc 7 max burst = 150
tc 7 update interval = 15
tc 7 tailq th = 64
tc 8 qdelay ref = 15
tc 8 max burst = 150
tc 8 update interval = 15
tc 8 tailq th = 64
tc 9 qdelay ref = 15
tc 9 max burst = 150
tc 9 update interval = 15
tc 9 tailq th = 64
tc 10 qdelay ref = 15
tc 10 max burst = 150
tc 10 update interval = 15
tc 10 tailq th = 64
tc 11 qdelay ref = 15
tc 11 max burst = 150
tc 11 update interval = 15
tc 11 tailq th = 64
tc 12 qdelay ref = 15
tc 12 max burst = 150
tc 12 update interval = 15
tc 12 tailq th = 64