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net/mlx5: fix integrity match on inner and outer headers

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MLX5 PMD can match on integrity bits for inner and outer headers in
a single flow.
That means a single flow rule can reference both inner and outer
integrity bits. That is implemented by adding 2 flow integrity items
to a rule - one item for outer integrity bits and other for
inner integrity bits.
Integrity item `level` parameter specifies what part is being
targeted.

Current PMD treated integrity items for outer and inner headers as
the same.
The patch separates PMD verifications for inner and outer integrity
items.

Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item")
Cc: stable@dpdk.org

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This commit is contained in:
Gregory Etelson 2021-10-26 12:25:42 +03:00 committed by Raslan Darawsheh
parent a7ac7fae49
commit 06741117ec
2 changed files with 26 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/net/mlx5/mlx5_flow.h
View File

@ -170,11 +170,12 @@ enum mlx5_feature_name {
#define MLX5_FLOW_LAYER_GENEVE_OPT (UINT64_C(1) << 32)
#define MLX5_FLOW_LAYER_GTP_PSC (UINT64_C(1) << 33)
/* INTEGRITY item bit */
#define MLX5_FLOW_ITEM_INTEGRITY (UINT64_C(1) << 34)
/* INTEGRITY item bits */
#define MLX5_FLOW_ITEM_OUTER_INTEGRITY (UINT64_C(1) << 34)
#define MLX5_FLOW_ITEM_INNER_INTEGRITY (UINT64_C(1) << 35)
/* Conntrack item. */
#define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 35)
#define MLX5_FLOW_LAYER_ASO_CT (UINT64_C(1) << 36)
/* Outer Masks. */
#define MLX5_FLOW_LAYER_OUTER_L3 \

29
drivers/net/mlx5/mlx5_flow_dv.c
View File

@ -6679,6 +6679,7 @@ static int
flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
const struct rte_flow_item *rule_items,
const struct rte_flow_item *integrity_item,
uint64_t item_flags, uint64_t *last_item,
struct rte_flow_error *error)
{
struct mlx5_priv *priv = dev->data->dev_private;
@ -6694,6 +6695,11 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
RTE_FLOW_ERROR_TYPE_ITEM,
integrity_item,
"packet integrity integrity_item not supported");
if (!spec)
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
integrity_item,
"no spec for integrity item");
if (!mask)
mask = &rte_flow_item_integrity_mask;
if (!mlx5_validate_integrity_item(mask))
@ -6703,6 +6709,11 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
"unsupported integrity filter");
tunnel_item = mlx5_flow_find_tunnel_item(rule_items);
if (spec->level > 1) {
if (item_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
return rte_flow_error_set
(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "multiple inner integrity items not supported");
if (!tunnel_item)
return rte_flow_error_set(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
@ -6711,6 +6722,11 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
item = tunnel_item;
end_item = mlx5_find_end_item(tunnel_item);
} else {
if (item_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
return rte_flow_error_set
(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "multiple outer integrity items not supported");
end_item = tunnel_item ? tunnel_item :
mlx5_find_end_item(integrity_item);
}
@ -6730,6 +6746,8 @@ flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
integrity_item,
"missing L4 protocol");
}
*last_item |= spec->level > 1 ? MLX5_FLOW_ITEM_INNER_INTEGRITY :
MLX5_FLOW_ITEM_OUTER_INTEGRITY;
return 0;
}
@ -7152,16 +7170,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
last_item = MLX5_FLOW_LAYER_ECPRI;
break;
case RTE_FLOW_ITEM_TYPE_INTEGRITY:
if (item_flags & MLX5_FLOW_ITEM_INTEGRITY)
return rte_flow_error_set
(error, ENOTSUP,
RTE_FLOW_ERROR_TYPE_ITEM,
NULL, "multiple integrity items not supported");
ret = flow_dv_validate_item_integrity(dev, rule_items,
items, error);
items,
item_flags,
&last_item,
error);
if (ret < 0)
return ret;
last_item = MLX5_FLOW_ITEM_INTEGRITY;
break;
case RTE_FLOW_ITEM_TYPE_CONNTRACK:
ret = flow_dv_validate_item_aso_ct(dev, items,