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common/qat: use write combining store for tail updates

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Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
This commit is contained in:
Radu Nicolau 2020-09-23 14:22:51 +00:00 committed by David Marchand
parent 0a65bf8d41
commit 0767e9eba1
2 changed files with 8 additions and 2 deletions
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4
doc/guides/rel_notes/release_20_11.rst
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@ -103,6 +103,10 @@ New Features
Updated the Intel i40e driver to use write combining stores.
* **Updated Intel qat driver.**
Updated the Intel qat driver to use write combining stores.
* **Added Ice Lake (Gen4) support for Intel NTB.**
Added NTB device support (4th generation) for Intel Ice Lake platform.

6
drivers/common/qat/qat_adf/adf_transport_access_macros.h
View File

@ -9,6 +9,8 @@
/* CSR write macro */
#define ADF_CSR_WR(csrAddr, csrOffset, val) \
rte_write32(val, (((uint8_t *)csrAddr) + csrOffset))
#define ADF_CSR_WC_WR(csrAddr, csrOffset, val) \
rte_write32_wc(val, (((uint8_t *)csrAddr) + csrOffset))
/* CSR read macro */
#define ADF_CSR_RD(csrAddr, csrOffset) \
@ -110,10 +112,10 @@ do { \
ADF_RING_CSR_RING_UBASE + (ring << 2), u_base); \
} while (0)
#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_RING_CSR_RING_HEAD + (ring << 2), value)
#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_CSR_WC_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
ADF_RING_CSR_RING_TAIL + (ring << 2), value)
#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
do { \