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net/mlx5: enable indexed pool per-core cache

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This commit enables the tag and header modify action indexed
pool per-core cache in non-reclaim memory mode.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is contained in:
Suanming Mou 2021-07-13 11:44:56 +03:00 committed by Raslan Darawsheh
parent f7c3f3c290
commit 07b51bb9fe
3 changed files with 6 additions and 2 deletions
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4
drivers/net/mlx5/mlx5.c
View File

@ -217,7 +217,8 @@ static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
.grow_trunk = 3,
.grow_shift = 2,
.need_lock = 1,
.release_mem_en = 1,
.release_mem_en = 0,
.per_core_cache = (1 << 16),
.malloc = mlx5_malloc,
.free = mlx5_free,
.type = "mlx5_tag_ipool",
@ -1129,6 +1130,7 @@ mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
}
sh->refcnt = 1;
sh->max_port = spawn->max_port;
sh->reclaim_mode = config->reclaim_mode;
strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
sizeof(sh->ibdev_name) - 1);
strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),

1
drivers/net/mlx5/mlx5.h
View File

@ -1118,6 +1118,7 @@ struct mlx5_dev_ctx_shared {
uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */
uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */
uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */
uint32_t reclaim_mode:1; /* Reclaim memory. */
uint32_t max_port; /* Maximal IB device port index. */
struct mlx5_bond_info bond; /* Bonding information. */
void *ctx; /* Verbs/DV/DevX context. */

3
drivers/net/mlx5/mlx5_flow_dv.c
View File

@ -5361,7 +5361,8 @@ flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
.grow_trunk = 3,
.grow_shift = 2,
.need_lock = 1,
.release_mem_en = 1,
.release_mem_en = !!sh->reclaim_mode,
.per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
.malloc = mlx5_malloc,
.free = mlx5_free,
.type = "mlx5_modify_action_resource",