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net/mlx5: support Tx interface query via DevX

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Implement function mlx5_devx_cmd_qp_tis_td_query(), to query
QP TIS Transport Domain value.

Add related structs in mlx5_prm.h.

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This commit is contained in:
Dekel Peled 2019-07-22 14:52:04 +00:00 committed by Ferruh Yigit
parent 175f1c21d0
commit 09f78f2144
3 changed files with 70 additions and 0 deletions
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2
drivers/net/mlx5/mlx5.h
View File

@ -737,4 +737,6 @@ int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
struct mlx5_devx_mkey_attr *attr);
int mlx5_devx_get_out_command_status(void *out);
int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
uint32_t *tis_td);
#endif /* RTE_PMD_MLX5_H_ */

34
drivers/net/mlx5/mlx5_devx_cmds.c
View File

@ -390,3 +390,37 @@ mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
rc = (rc > 0) ? -rc : rc;
return rc;
}
/**
* Query TIS transport domain from QP verbs object using DevX API.
*
* @param[in] qp
* Pointer to verbs QP returned by ibv_create_qp .
* @param[in] tis_num
* TIS number of TIS to query.
* @param[out] tis_td
* Pointer to TIS transport domain variable, to be set by the routine.
*
* @return
* 0 on success, a negative value otherwise.
*/
int
mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
uint32_t *tis_td)
{
uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
int rc;
void *tis_ctx;
MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
MLX5_SET(query_tis_in, in, tisn, tis_num);
rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
if (rc) {
DRV_LOG(ERR, "Failed to query QP using DevX");
return -rc;
};
tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
*tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
return 0;
}

34
drivers/net/mlx5/mlx5_prm.h
View File

@ -627,6 +627,7 @@ enum {
MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
MLX5_CMD_OP_CREATE_MKEY = 0x200,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
};
@ -1234,6 +1235,39 @@ struct mlx5_ifc_query_nic_vport_context_in_bits {
u8 reserved_at_68[0x18];
};
struct mlx5_ifc_tisc_bits {
u8 strict_lag_tx_port_affinity[0x1];
u8 reserved_at_1[0x3];
u8 lag_tx_port_affinity[0x04];
u8 reserved_at_8[0x4];
u8 prio[0x4];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x100];
u8 reserved_at_120[0x8];
u8 transport_domain[0x18];
u8 reserved_at_140[0x8];
u8 underlay_qpn[0x18];
u8 reserved_at_160[0x3a0];
};
struct mlx5_ifc_query_tis_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
struct mlx5_ifc_tisc_bits tis_context;
};
struct mlx5_ifc_query_tis_in_bits {
u8 opcode[0x10];
u8 reserved_at_10[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0x8];
u8 tisn[0x18];
u8 reserved_at_60[0x20];
};
/* CQE format mask. */
#define MLX5E_CQE_FORMAT_MASK 0xc