crypto/nitrox: introduce Nitrox driver

Add bare minimum Nitrox PMD library which handles pci probe, remove and
hardware initialization. Add logs, documentation and update maintainers
file.

Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>

MAINTAINERS

@@ -963,6 +963,13 @@ F: drivers/crypto/mvsam/
 F: doc/guides/cryptodevs/mvsam.rst
 F: doc/guides/cryptodevs/features/mvsam.ini
 
+Marvell Nitrox
+M: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
+M: Srikanth Jampala <jsrikanth@marvell.com>
+F: drivers/crypto/nitrox/
+F: doc/guides/cryptodevs/nitrox.rst
+F: doc/guides/cryptodevs/features/nitrox.ini
+
 Null Crypto
 M: Declan Doherty <declan.doherty@intel.com>
 F: drivers/crypto/null/

config/common_base

@@ -663,6 +663,11 @@ CONFIG_RTE_LIBRTE_PMD_CCP=n
 #
 CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n
 
+#
+# Compile PMD for NITROX crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_NITROX=y
+
 #
 # Compile generic security library
 #

doc/guides/cryptodevs/index.rst

@@ -21,6 +21,7 @@ Crypto Device Drivers
     octeontx
     openssl
     mvsam
+    nitrox
     null
     scheduler
     snow3g

doc/guides/cryptodevs/nitrox.rst

@@ -0,0 +1,30 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(C) 2019 Marvell International Ltd.
+
+Marvell NITROX Crypto Poll Mode Driver
+======================================
+
+The Nitrox crypto poll mode driver provides support for offloading
+cryptographic operations to the NITROX V security processor. Detailed
+information about the NITROX V security processor can be obtained here:
+
+* https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/
+
+Installation
+------------
+
+For compiling the Nitrox crypto PMD, please check if the
+CONFIG_RTE_LIBRTE_PMD_NITROX setting is set to `y` in config/common_base file.
+
+* ``CONFIG_RTE_LIBRTE_PMD_NITROX=y``
+
+Initialization
+--------------
+
+Nitrox crypto PMD depend on Nitrox kernel PF driver being installed on the
+platform. Nitrox PF driver is required to create VF devices which will
+be used by the PMD. Each VF device can enable one cryptodev PMD.
+
+Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK
+and it's installation instructions can be obtained from:
+`Marvell Technical Documentation Portal <https://support.cavium.com/>`_.

drivers/crypto/Makefile

@@ -25,5 +25,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) += caam_jr
 endif # CONFIG_RTE_LIBRTE_PMD_DPAA_SEC
 endif # CONFIG_RTE_LIBRTE_SECURITY
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) += virtio
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox
 
 include $(RTE_SDK)/mk/rte.subdir.mk

drivers/crypto/meson.build

@@ -2,8 +2,8 @@
 # Copyright(c) 2017 Intel Corporation
 
 drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',
-	'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler',
-	'snow3g', 'virtio', 'zuc']
+	'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat',
+	'scheduler', 'snow3g', 'virtio', 'zuc']
 
 std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
 config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'

drivers/crypto/nitrox/Makefile

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_nitrox.a
+
+# build flags
+CFLAGS += -O3
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -DALLOW_EXPERIMENTAL_API
+
+# library version
+LIBABIVER := 1
+
+# versioning export map
+EXPORT_MAP := rte_pmd_nitrox_version.map
+
+# external library dependencies
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool
+LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_cryptodev
+
+# library source files
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c
+
+include $(RTE_SDK)/mk/rte.lib.mk

drivers/crypto/nitrox/meson.build

@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2019 Marvell International Ltd.
+
+if not is_linux
+	build = false
+	reason = 'only supported on Linux'
+endif
+
+deps += ['bus_pci']
+allow_experimental_apis = true
+sources = files(
+		'nitrox_device.c',
+		'nitrox_hal.c',
+		'nitrox_logs.c',
+		)

drivers/crypto/nitrox/nitrox_csr.h

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _NITROX_CSR_H_
+#define _NITROX_CSR_H_
+
+#include <rte_common.h>
+#include <rte_io.h>
+
+#define CSR_DELAY	30
+
+/* AQM Virtual Function Registers */
+#define AQMQ_QSZX(_i)			(0x20008 + ((_i)*0x40000))
+
+static inline uint64_t
+nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)
+{
+	return rte_read64(bar_addr + offset);
+}
+
+static inline void
+nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value)
+{
+	rte_write64(value, (bar_addr + offset));
+}
+
+#endif /* _NITROX_CSR_H_ */

drivers/crypto/nitrox/nitrox_device.c

@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_malloc.h>
+
+#include "nitrox_device.h"
+#include "nitrox_hal.h"
+
+#define PCI_VENDOR_ID_CAVIUM	0x177d
+#define NITROX_V_PCI_VF_DEV_ID	0x13
+
+TAILQ_HEAD(ndev_list, nitrox_device);
+static struct ndev_list ndev_list = TAILQ_HEAD_INITIALIZER(ndev_list);
+
+static struct nitrox_device *
+ndev_allocate(struct rte_pci_device *pdev)
+{
+	struct nitrox_device *ndev;
+
+	ndev = rte_zmalloc_socket("nitrox device", sizeof(*ndev),
+				   RTE_CACHE_LINE_SIZE,
+				   pdev->device.numa_node);
+	if (!ndev)
+		return NULL;
+
+	TAILQ_INSERT_TAIL(&ndev_list, ndev, next);
+	return ndev;
+}
+
+static void
+ndev_init(struct nitrox_device *ndev, struct rte_pci_device *pdev)
+{
+	enum nitrox_vf_mode vf_mode;
+
+	ndev->pdev = pdev;
+	ndev->bar_addr = pdev->mem_resource[0].addr;
+	vf_mode = vf_get_vf_config_mode(ndev->bar_addr);
+	ndev->nr_queues = vf_config_mode_to_nr_queues(vf_mode);
+}
+
+static struct nitrox_device *
+find_ndev(struct rte_pci_device *pdev)
+{
+	struct nitrox_device *ndev;
+
+	TAILQ_FOREACH(ndev, &ndev_list, next)
+		if (ndev->pdev == pdev)
+			return ndev;
+
+	return NULL;
+}
+
+static void
+ndev_release(struct nitrox_device *ndev)
+{
+	if (!ndev)
+		return;
+
+	TAILQ_REMOVE(&ndev_list, ndev, next);
+	rte_free(ndev);
+}
+
+static int
+nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+		struct rte_pci_device *pdev)
+{
+	struct nitrox_device *ndev;
+
+	/* Nitrox CSR space */
+	if (!pdev->mem_resource[0].addr)
+		return -EINVAL;
+
+	ndev = ndev_allocate(pdev);
+	if (!ndev)
+		return -ENOMEM;
+
+	ndev_init(ndev, pdev);
+	return 0;
+}
+
+static int
+nitrox_pci_remove(struct rte_pci_device *pdev)
+{
+	struct nitrox_device *ndev;
+
+	ndev = find_ndev(pdev);
+	if (!ndev)
+		return -ENODEV;
+
+	ndev_release(ndev);
+	return 0;
+}
+
+static struct rte_pci_id pci_id_nitrox_map[] = {
+	{
+		/* Nitrox 5 VF */
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, NITROX_V_PCI_VF_DEV_ID)
+	},
+	{.device_id = 0},
+};
+
+static struct rte_pci_driver nitrox_pmd = {
+	.id_table       = pci_id_nitrox_map,
+	.drv_flags      = RTE_PCI_DRV_NEED_MAPPING,
+	.probe          = nitrox_pci_probe,
+	.remove         = nitrox_pci_remove,
+};
+
+RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map);

drivers/crypto/nitrox/nitrox_device.h

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _NITROX_DEVICE_H_
+#define _NITROX_DEVICE_H_
+
+#include <rte_bus_pci.h>
+#include <rte_cryptodev.h>
+
+struct nitrox_device {
+	TAILQ_ENTRY(nitrox_device) next;
+	struct rte_pci_device *pdev;
+	uint8_t *bar_addr;
+	uint16_t nr_queues;
+};
+
+#endif /* _NITROX_DEVICE_H_ */

drivers/crypto/nitrox/nitrox_hal.c

@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_common.h>
+#include <rte_cycles.h>
+#include <rte_memory.h>
+#include <rte_byteorder.h>
+
+#include "nitrox_hal.h"
+#include "nitrox_csr.h"
+
+#define MAX_VF_QUEUES	8
+#define MAX_PF_QUEUES	64
+
+int
+vf_get_vf_config_mode(uint8_t *bar_addr)
+{
+	union aqmq_qsz aqmq_qsz;
+	uint64_t reg_addr;
+	int q, vf_mode;
+
+	aqmq_qsz.u64 = 0;
+	aqmq_qsz.s.host_queue_size = 0xDEADBEEF;
+	reg_addr = AQMQ_QSZX(0);
+	nitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64);
+	rte_delay_us_block(CSR_DELAY);
+
+	aqmq_qsz.u64 = 0;
+	for (q = 1; q < MAX_VF_QUEUES; q++) {
+		reg_addr = AQMQ_QSZX(q);
+		aqmq_qsz.u64 = nitrox_read_csr(bar_addr, reg_addr);
+		if (aqmq_qsz.s.host_queue_size == 0xDEADBEEF)
+			break;
+	}
+
+	switch (q) {
+	case 1:
+		vf_mode = NITROX_MODE_VF128;
+		break;
+	case 2:
+		vf_mode = NITROX_MODE_VF64;
+		break;
+	case 4:
+		vf_mode = NITROX_MODE_VF32;
+		break;
+	case 8:
+		vf_mode = NITROX_MODE_VF16;
+		break;
+	default:
+		vf_mode = 0;
+		break;
+	}
+
+	return vf_mode;
+}
+
+int
+vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode)
+{
+	int nr_queues;
+
+	switch (vf_mode) {
+	case NITROX_MODE_PF:
+		nr_queues = MAX_PF_QUEUES;
+		break;
+	case NITROX_MODE_VF16:
+		nr_queues = 8;
+		break;
+	case NITROX_MODE_VF32:
+		nr_queues = 4;
+		break;
+	case NITROX_MODE_VF64:
+		nr_queues = 2;
+		break;
+	case NITROX_MODE_VF128:
+		nr_queues = 1;
+		break;
+	default:
+		nr_queues = 0;
+		break;
+	}
+
+	return nr_queues;
+}

drivers/crypto/nitrox/nitrox_hal.h

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _NITROX_HAL_H_
+#define _NITROX_HAL_H_
+
+#include <rte_cycles.h>
+#include <rte_byteorder.h>
+
+#include "nitrox_csr.h"
+
+union aqmq_qsz {
+	uint64_t u64;
+	struct {
+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
+		uint64_t raz : 32;
+		uint64_t host_queue_size : 32;
+#else
+		uint64_t host_queue_size : 32;
+		uint64_t raz : 32;
+#endif
+	} s;
+};
+
+enum nitrox_vf_mode {
+	NITROX_MODE_PF = 0x0,
+	NITROX_MODE_VF16 = 0x1,
+	NITROX_MODE_VF32 = 0x2,
+	NITROX_MODE_VF64 = 0x3,
+	NITROX_MODE_VF128 = 0x4,
+};
+
+int vf_get_vf_config_mode(uint8_t *bar_addr);
+int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode);
+
+#endif /* _NITROX_HAL_H_ */

drivers/crypto/nitrox/nitrox_logs.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_log.h>
+
+int nitrox_logtype;
+
+RTE_INIT(nitrox_init_log)
+{
+	nitrox_logtype = rte_log_register("pmd.crypto.nitrox");
+	if (nitrox_logtype >= 0)
+		rte_log_set_level(nitrox_logtype, RTE_LOG_NOTICE);
+}

drivers/crypto/nitrox/nitrox_logs.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _NITROX_LOGS_H_
+#define _NITROX_LOGS_H_
+
+#define LOG_PREFIX "NITROX: "
+#define NITROX_LOG(level, fmt, args...)					\
+	rte_log(RTE_LOG_ ## level, nitrox_logtype,			\
+		LOG_PREFIX "%s:%d " fmt, __func__, __LINE__, ## args)
+
+extern int nitrox_logtype;
+
+#endif /* _NITROX_LOGS_H_ */

drivers/crypto/nitrox/rte_pmd_nitrox_version.map

@@ -0,0 +1,3 @@
+DPDK_19.11 {
+	local: *;
+};

mk/rte.app.mk

@@ -267,6 +267,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ZUC)         += -L$(LIBSSO_ZUC_PATH)/build -lsso
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -lrte_pmd_armv8
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NITROX)      += -lrte_pmd_nitrox
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
 ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y)