crypto/cnxk: add ZUC and SNOW3G decryption
Add PDCP opcode which handles ZUC and SNOW3G. Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com> Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Archana Muniganti <marchana@marvell.com> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com> Acked-by: Akhil Goyal <gakhil@marvell.com>
This commit is contained in:
Tejasree Kondoj
Akhil Goyal
parent
8a8aa448aa
commit
0c83c9abb9
@ -30,6 +30,8 @@ AES CTR (256) = Y
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AES XTS (128) = Y
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AES XTS (256) = Y
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DES CBC = Y
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SNOW3G UEA2 = Y
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ZUC EEA3 = Y
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;
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; Supported authentication algorithms of 'cn10k' crypto driver.
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@ -30,6 +30,8 @@ AES CTR (256) = Y
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AES XTS (128) = Y
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AES XTS (256) = Y
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DES CBC = Y
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SNOW3G UEA2 = Y
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ZUC EEA3 = Y
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;
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; Supported authentication algorithms of 'cn9k' crypto driver.
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@ -1078,6 +1078,209 @@ cpt_zuc_snow3g_enc_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
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return 0;
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}
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static __rte_always_inline int
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cpt_zuc_snow3g_dec_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens,
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struct roc_se_fc_params *params,
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struct cpt_inst_s *inst)
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{
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uint32_t size;
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int32_t inputlen = 0, outputlen;
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struct roc_se_ctx *se_ctx;
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uint8_t pdcp_alg_type, iv_len = 16;
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uint32_t encr_offset;
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uint32_t encr_data_len;
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int flags;
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uint64_t *offset_vaddr;
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uint32_t *iv_s, iv[4], j;
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union cpt_inst_w4 cpt_inst_w4;
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/*
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* Microcode expects offsets in bytes
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* TODO: Rounding off
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*/
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encr_offset = ROC_SE_ENCR_OFFSET(d_offs) / 8;
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encr_data_len = ROC_SE_ENCR_DLEN(d_lens);
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se_ctx = params->ctx_buf.vaddr;
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flags = se_ctx->zsk_flags;
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pdcp_alg_type = se_ctx->pdcp_alg_type;
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cpt_inst_w4.u64 = 0;
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cpt_inst_w4.s.opcode_major = ROC_SE_MAJOR_OP_ZUC_SNOW3G;
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/* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
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cpt_inst_w4.s.opcode_minor = ((1 << 7) | (pdcp_alg_type << 5) |
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(0 << 4) | (0 << 3) | (flags & 0x7));
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/* consider iv len */
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encr_offset += iv_len;
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inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
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outputlen = inputlen;
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/* IV */
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iv_s = params->iv_buf;
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if (pdcp_alg_type == ROC_SE_PDCP_ALG_TYPE_SNOW3G) {
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/*
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* DPDK seems to provide it in form of IV3 IV2 IV1 IV0
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* and BigEndian, MC needs it as IV0 IV1 IV2 IV3
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*/
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for (j = 0; j < 4; j++)
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iv[j] = iv_s[3 - j];
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} else {
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/* ZUC doesn't need a swap */
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for (j = 0; j < 4; j++)
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iv[j] = iv_s[j];
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}
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/*
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* GP op header, lengths are expected in bits.
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*/
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cpt_inst_w4.s.param1 = encr_data_len;
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/*
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* In cn9k, cn10k since we have a limitation of
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* IV & Offset control word not part of instruction
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* and need to be part of Data Buffer, we check if
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* head room is there and then only do the Direct mode processing
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*/
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if (likely((req_flags & ROC_SE_SINGLE_BUF_INPLACE) &&
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(req_flags & ROC_SE_SINGLE_BUF_HEADROOM))) {
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void *dm_vaddr = params->bufs[0].vaddr;
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/* Use Direct mode */
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offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
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ROC_SE_OFF_CTRL_LEN - iv_len);
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/* DPTR */
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inst->dptr = (uint64_t)offset_vaddr;
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/* RPTR should just exclude offset control word */
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inst->rptr = (uint64_t)dm_vaddr - iv_len;
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cpt_inst_w4.s.dlen = inputlen + ROC_SE_OFF_CTRL_LEN;
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if (likely(iv_len)) {
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uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
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ROC_SE_OFF_CTRL_LEN);
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memcpy(iv_d, iv, 16);
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}
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/* iv offset is 0 */
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*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
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} else {
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void *m_vaddr = params->meta_buf.vaddr;
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uint32_t i, g_size_bytes, s_size_bytes;
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struct roc_se_sglist_comp *gather_comp;
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struct roc_se_sglist_comp *scatter_comp;
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uint8_t *in_buffer;
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uint32_t *iv_d;
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/* save space for offset and iv... */
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offset_vaddr = m_vaddr;
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m_vaddr = (uint8_t *)m_vaddr + ROC_SE_OFF_CTRL_LEN + iv_len;
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cpt_inst_w4.s.opcode_major |= (uint64_t)ROC_SE_DMA_MODE;
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/* DPTR has SG list */
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in_buffer = m_vaddr;
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((uint16_t *)in_buffer)[0] = 0;
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((uint16_t *)in_buffer)[1] = 0;
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/* TODO Add error check if space will be sufficient */
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gather_comp =
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(struct roc_se_sglist_comp *)((uint8_t *)m_vaddr + 8);
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/*
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* Input Gather List
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*/
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i = 0;
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/* Offset control word */
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/* iv offset is 0 */
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*offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
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i = fill_sg_comp(gather_comp, i, (uint64_t)offset_vaddr,
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ROC_SE_OFF_CTRL_LEN + iv_len);
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iv_d = (uint32_t *)((uint8_t *)offset_vaddr +
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ROC_SE_OFF_CTRL_LEN);
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memcpy(iv_d, iv, 16);
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/* Add input data */
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size = inputlen - iv_len;
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if (size) {
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i = fill_sg_comp_from_iov(gather_comp, i,
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params->src_iov, 0, &size,
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NULL, 0);
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if (unlikely(size)) {
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plt_dp_err("Insufficient buffer space,"
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" size %d needed",
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size);
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return -1;
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}
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}
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((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
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g_size_bytes =
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((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);
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/*
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* Output Scatter List
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*/
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i = 0;
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scatter_comp =
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(struct roc_se_sglist_comp *)((uint8_t *)gather_comp +
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g_size_bytes);
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/* IV */
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i = fill_sg_comp(scatter_comp, i,
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(uint64_t)offset_vaddr + ROC_SE_OFF_CTRL_LEN,
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iv_len);
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/* Add output data */
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size = outputlen - iv_len;
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if (size) {
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i = fill_sg_comp_from_iov(scatter_comp, i,
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params->dst_iov, 0, &size,
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NULL, 0);
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if (unlikely(size)) {
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plt_dp_err("Insufficient buffer space,"
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" size %d needed",
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size);
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return -1;
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}
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}
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((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
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s_size_bytes =
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((i + 3) / 4) * sizeof(struct roc_se_sglist_comp);
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size = g_size_bytes + s_size_bytes + ROC_SE_SG_LIST_HDR_SIZE;
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/* This is DPTR len in case of SG mode */
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cpt_inst_w4.s.dlen = size;
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inst->dptr = (uint64_t)in_buffer;
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}
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if (unlikely((encr_offset >> 16))) {
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plt_dp_err("Offset not supported");
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plt_dp_err("enc_offset: %d", encr_offset);
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return -1;
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}
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inst->w4.u64 = cpt_inst_w4.u64;
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return 0;
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}
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static __rte_always_inline int
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cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
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struct roc_se_fc_params *fc_params,
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@ -1089,8 +1292,12 @@ cpt_fc_dec_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
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fc_type = ctx->fc_type;
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if (likely(fc_type == ROC_SE_FC_GEN))
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if (likely(fc_type == ROC_SE_FC_GEN)) {
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ret = cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, inst);
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} else if (fc_type == ROC_SE_PDCP) {
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ret = cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params,
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inst);
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}
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return ret;
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}
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