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ixgbe/base: set MDIO speed after MAC reset

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The MDIO clock speed must be reconfigured after the MAC reset.
The MDIO clock speed becomes invalid, therefore the driver reads
invalid PHY register values. The driver now set the MDIO clock
speed prior to initializing PHY ops and again after the MAC reset.

As now the MDIO speed gets set in more than one place, make a
function for it so it will always be done correctly.

Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
This commit is contained in:
Wenzhuo Lu 2016-02-14 16:55:03 +08:00 committed by Thomas Monjalon
parent e2f368a4bf
commit 0cf7c6a6f3
2 changed files with 35 additions and 7 deletions
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7
doc/guides/rel_notes/release_16_04.rst
View File

@ -193,6 +193,13 @@ Drivers
Resolved an issue where packets were being dropped when switching to perfect
filters mode.
* **ixgbe: Set MDIO speed after MAC reset.**
The MDIO clock speed must be reconfigured after the MAC reset. The MDIO clock
speed becomes invalid, therefore the driver reads invalid PHY register values.
The driver now set the MDIO clock speed prior to initializing PHY ops and
again after the MAC reset.
* **aesni_mb: Fixed wrong return value when creating a device.**
cryptodev_aesni_mb_init() was returning the device id of the device created,

35
drivers/net/ixgbe/base/ixgbe_x550.c
View File

@ -1678,6 +1678,31 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
return ret_val;
}
/**
* ixgbe_set_mdio_speed - Set MDIO clock speed
* @hw: pointer to hardware structure
*/
static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
{
u32 hlreg0;
switch (hw->device_id) {
case IXGBE_DEV_ID_X550EM_X_10G_T:
case IXGBE_DEV_ID_X550EM_A_1G_T:
case IXGBE_DEV_ID_X550EM_A_1G_T_L:
case IXGBE_DEV_ID_X550EM_A_10G_T:
case IXGBE_DEV_ID_X550EM_A_SFP:
case IXGBE_DEV_ID_X550EM_A_QSFP:
/* Config MDIO clock speed before the first MDIO PHY access */
hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
break;
default:
break;
}
}
/**
* ixgbe_reset_hw_X550em - Perform hardware reset
* @hw: pointer to hardware structure
@ -1692,7 +1717,6 @@ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
s32 status;
u32 ctrl = 0;
u32 i;
u32 hlreg0;
bool link_up = false;
DEBUGFUNC("ixgbe_reset_hw_X550em");
@ -1705,12 +1729,7 @@ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
/* flush pending Tx transactions */
ixgbe_clear_tx_pending(hw);
if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) {
/* Config MDIO clock speed before the first MDIO PHY access */
hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
}
ixgbe_set_mdio_speed(hw);
/* PHY ops must be identified and initialized prior to reset */
status = hw->phy.ops.init(hw);
@ -1789,6 +1808,8 @@ mac_reset_top:
hw->mac.num_rar_entries = 128;
hw->mac.ops.init_rx_addrs(hw);
ixgbe_set_mdio_speed(hw);
if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
ixgbe_setup_mux_ctl(hw);