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net/mlx5: use coherent I/O memory barrier

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Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
This commit is contained in:
Yongseok Koh 2018-05-11 18:35:44 -07:00 committed by Ferruh Yigit
parent 5f44cfd011
commit 0cfdc1808d
1 changed files with 2 additions and 2 deletions
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4
drivers/net/mlx5/mlx5_rxtx.c
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@ -2253,11 +2253,11 @@ mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
}
/* Update the consumer indexes. */
rxq->strd_ci = strd_idx;
rte_io_wmb();
rte_cio_wmb();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
if (rq_ci != rxq->rq_ci) {
rxq->rq_ci = rq_ci;
rte_io_wmb();
rte_cio_wmb();
*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
}
#ifdef MLX5_PMD_SOFT_COUNTERS