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crypto/octeontx: add hardware init routine

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Adding hardware init routine for OCTEON TX crypto device. A place holder
is added for misc polling routine. That will be added in the further
patches.

Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
This commit is contained in:
Ankur Dwivedi 2018-10-09 14:37:35 +05:30 committed by Akhil Goyal
parent bfe2ae495e
commit 0dc1cffa4d
6 changed files with 322 additions and 1 deletions
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47
drivers/common/cpt/cpt_common.h Normal file
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@ -0,0 +1,47 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2018 Cavium, Inc
*/
#ifndef _CPT_COMMON_H_
#define _CPT_COMMON_H_
/*
* This file defines common macros and structs
*/
/*
* Macros to determine CPT model. Driver makefile will define CPT_MODEL
* accordingly
*/
#define CRYPTO_OCTEONTX 0x1
#define AE_TYPE 1
#define SE_TYPE 2
struct cptvf_meta_info {
void *cptvf_meta_pool;
int cptvf_op_mlen;
int cptvf_op_sb_mlen;
};
struct rid {
/** Request id of a crypto operation */
uintptr_t rid;
};
/*
* Pending queue structure
*
*/
struct pending_queue {
/** Tail of queue to be used for enqueue */
uint16_t enq_tail;
/** Head of queue to be used for dequeue */
uint16_t deq_head;
/** Array of pending requests */
struct rid *rid_queue;
/** Pending requests count */
uint64_t pending_count;
};
#endif /* _CPT_COMMON_H_ */

1
drivers/crypto/octeontx/Makefile
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@ -24,6 +24,7 @@ CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
# PMD code
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_hw_access.c
SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += otx_cryptodev_ops.c
# export include files

1
drivers/crypto/octeontx/meson.build
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@ -8,6 +8,7 @@ deps += ['bus_pci']
name = 'octeontx_crypto'
sources = files('otx_cryptodev.c',
'otx_cryptodev_hw_access.c',
'otx_cryptodev_ops.c')
cflags += '-DCPT_MODEL=CRYPTO_OCTEONTX'

48
drivers/crypto/octeontx/otx_cryptodev_hw_access.c Normal file
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@ -0,0 +1,48 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2018 Cavium, Inc
*/
#include <string.h>
#include <rte_common.h>
#include "otx_cryptodev_hw_access.h"
#include "cpt_pmd_logs.h"
static int
otx_cpt_vf_init(struct cpt_vf *cptvf)
{
int ret = 0;
CPT_LOG_DP_DEBUG("%s: %s done", cptvf->dev_name, __func__);
return ret;
}
void
otx_cpt_poll_misc(struct cpt_vf *cptvf)
{
RTE_SET_USED(cptvf);
}
int
otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name)
{
memset(cptvf, 0, sizeof(struct cpt_vf));
/* Bar0 base address */
cptvf->reg_base = reg_base;
strncpy(cptvf->dev_name, name, 32);
cptvf->pdev = pdev;
/* To clear if there are any pending mbox msgs */
otx_cpt_poll_misc(cptvf);
if (otx_cpt_vf_init(cptvf)) {
CPT_LOG_ERR("Failed to initialize CPT VF device");
return -1;
}
return 0;
}

134
drivers/crypto/octeontx/otx_cryptodev_hw_access.h Normal file
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@ -0,0 +1,134 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2018 Cavium, Inc
*/
#ifndef _OTX_CRYPTODEV_HW_ACCESS_H_
#define _OTX_CRYPTODEV_HW_ACCESS_H_
#include <stdbool.h>
#include <rte_memory.h>
#include "cpt_common.h"
#define CPT_INTR_POLL_INTERVAL_MS (50)
/* Default command queue length */
#define DEFAULT_CMD_QCHUNKS 2
/* cpt instance */
struct cpt_instance {
uint32_t queue_id;
uintptr_t rsvd;
};
struct command_chunk {
/** 128-byte aligned real_vaddr */
uint8_t *head;
/** 128-byte aligned real_dma_addr */
phys_addr_t dma_addr;
};
/**
* Command queue structure
*/
struct command_queue {
/** Command queue host write idx */
uint32_t idx;
/** Command queue chunk */
uint32_t cchunk;
/** Command queue head; instructions are inserted here */
uint8_t *qhead;
/** Command chunk list head */
struct command_chunk chead[DEFAULT_CMD_QCHUNKS];
};
/**
* CPT VF device structure
*/
struct cpt_vf {
/** CPT instance */
struct cpt_instance instance;
/** Register start address */
uint8_t *reg_base;
/** Command queue information */
struct command_queue cqueue;
/** Pending queue information */
struct pending_queue pqueue;
/** Meta information per vf */
struct cptvf_meta_info meta_info;
/** Below fields are accessed only in control path */
/** Env specific pdev representing the pci dev */
void *pdev;
/** Calculated queue size */
uint32_t qsize;
/** Device index (0...CPT_MAX_VQ_NUM)*/
uint8_t vfid;
/** VF type of cpt_vf_type_t (SE_TYPE(2) or AE_TYPE(1) */
uint8_t vftype;
/** VF group (0 - 8) */
uint8_t vfgrp;
/** Operating node: Bits (46:44) in BAR0 address */
uint8_t node;
/** VF-PF mailbox communication */
/** Flag if acked */
bool pf_acked;
/** Flag if not acked */
bool pf_nacked;
/** Device name */
char dev_name[32];
} __rte_cache_aligned;
/*
* CPT Registers map for 81xx
*/
/* VF registers */
#define CPTX_VQX_CTL(a, b) (0x0000100ll + 0x1000000000ll * \
((a) & 0x0) + 0x100000ll * (b))
#define CPTX_VQX_SADDR(a, b) (0x0000200ll + 0x1000000000ll * \
((a) & 0x0) + 0x100000ll * (b))
#define CPTX_VQX_DONE_WAIT(a, b) (0x0000400ll + 0x1000000000ll * \
((a) & 0x0) + 0x100000ll * (b))
#define CPTX_VQX_INPROG(a, b) (0x0000410ll + 0x1000000000ll * \
((a) & 0x0) + 0x100000ll * (b))
#define CPTX_VQX_DONE(a, b) (0x0000420ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_DONE_ACK(a, b) (0x0000440ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_DONE_INT_W1S(a, b) (0x0000460ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_DONE_INT_W1C(a, b) (0x0000468ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_DONE_ENA_W1S(a, b) (0x0000470ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_DONE_ENA_W1C(a, b) (0x0000478ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_MISC_INT(a, b) (0x0000500ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_MISC_INT_W1S(a, b) (0x0000508ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_MISC_ENA_W1S(a, b) (0x0000510ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_MISC_ENA_W1C(a, b) (0x0000518ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VQX_DOORBELL(a, b) (0x0000600ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b))
#define CPTX_VFX_PF_MBOXX(a, b, c) (0x0001000ll + 0x1000000000ll * \
((a) & 0x1) + 0x100000ll * (b) + \
8ll * ((c) & 0x1))
/* VF HAL functions */
void
otx_cpt_poll_misc(struct cpt_vf *cptvf);
int
otx_cpt_hw_init(struct cpt_vf *cptvf, void *pdev, void *reg_base, char *name);
#endif /* _OTX_CRYPTODEV_HW_ACCESS_H_ */

92
drivers/crypto/octeontx/otx_cryptodev_ops.c
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@ -2,14 +2,104 @@
* Copyright(c) 2018 Cavium, Inc
*/
#include <rte_alarm.h>
#include <rte_bus_pci.h>
#include <rte_cryptodev.h>
#include <rte_malloc.h>
#include "cpt_pmd_logs.h"
#include "otx_cryptodev.h"
#include "otx_cryptodev_hw_access.h"
#include "otx_cryptodev_ops.h"
/* Alarm routines */
static void
otx_cpt_alarm_cb(void *arg)
{
struct cpt_vf *cptvf = arg;
otx_cpt_poll_misc(cptvf);
rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
otx_cpt_alarm_cb, cptvf);
}
static int
otx_cpt_periodic_alarm_start(void *arg)
{
return rte_eal_alarm_set(CPT_INTR_POLL_INTERVAL_MS * 1000,
otx_cpt_alarm_cb, arg);
}
int
otx_cpt_dev_create(struct rte_cryptodev *c_dev)
{
RTE_SET_USED(c_dev);
struct rte_pci_device *pdev = RTE_DEV_TO_PCI(c_dev->device);
struct cpt_vf *cptvf = NULL;
void *reg_base;
char dev_name[32];
int ret;
if (pdev->mem_resource[0].phys_addr == 0ULL)
return -EIO;
/* for secondary processes, we don't initialise any further as primary
* has already done this work.
*/
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
cptvf = rte_zmalloc_socket("otx_cryptodev_private_mem",
sizeof(struct cpt_vf), RTE_CACHE_LINE_SIZE,
rte_socket_id());
if (cptvf == NULL) {
CPT_LOG_ERR("Cannot allocate memory for device private data");
return -ENOMEM;
}
snprintf(dev_name, 32, "%02x:%02x.%x",
pdev->addr.bus, pdev->addr.devid, pdev->addr.function);
reg_base = pdev->mem_resource[0].addr;
if (!reg_base) {
CPT_LOG_ERR("Failed to map BAR0 of %s", dev_name);
ret = -ENODEV;
goto fail;
}
ret = otx_cpt_hw_init(cptvf, pdev, reg_base, dev_name);
if (ret) {
CPT_LOG_ERR("Failed to init cptvf %s", dev_name);
ret = -EIO;
goto fail;
}
/* Start off timer for mailbox interrupts */
otx_cpt_periodic_alarm_start(cptvf);
c_dev->dev_ops = NULL;
c_dev->enqueue_burst = NULL;
c_dev->dequeue_burst = NULL;
c_dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
RTE_CRYPTODEV_FF_HW_ACCELERATED |
RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
RTE_CRYPTODEV_FF_IN_PLACE_SGL |
RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
/* Save dev private data */
c_dev->data->dev_private = cptvf;
return 0;
fail:
if (cptvf) {
/* Free private data allocated */
rte_free(cptvf);
}
return ret;
}