baseband/fpga_5gnr_fec: add debug functionality
Adding functionality for debug mode to be more verbose and catch error from unsupported configuration. Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com> Acked-by: Dave Burley <dave.burley@accelercomm.com> Acked-by: Niall Power <niall.power@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This commit is contained in:
Nicolas Chautru
Akhil Goyal
parent
bee09be327
commit
11b0a11245
@ -355,4 +355,34 @@ fpga_reg_read_32(void *mmio_base, uint32_t offset)
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return rte_le_to_cpu_32(ret);
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}
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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/* Read a register of FPGA 5GNR FEC device */
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static inline uint16_t
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fpga_reg_read_16(void *mmio_base, uint32_t offset)
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{
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void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
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uint16_t ret = *((volatile uint16_t *)(reg_addr));
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return rte_le_to_cpu_16(ret);
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}
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/* Read a register of FPGA 5GNR FEC device */
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static inline uint8_t
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fpga_reg_read_8(void *mmio_base, uint32_t offset)
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{
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void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
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return *((volatile uint8_t *)(reg_addr));
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}
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/* Read a register of FPGA 5GNR FEC device */
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static inline uint64_t
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fpga_reg_read_64(void *mmio_base, uint32_t offset)
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{
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void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
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uint64_t ret = *((volatile uint64_t *)(reg_addr));
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return rte_le_to_cpu_64(ret);
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}
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#endif
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#endif /* _FPGA_5GNR_FEC_H_ */
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@ -25,6 +25,161 @@
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/* 5GNR SW PMD logging ID */
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static int fpga_5gnr_fec_logtype;
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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/* Read Ring Control Register of FPGA 5GNR FEC device */
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static inline void
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print_ring_reg_debug_info(void *mmio_base, uint32_t offset)
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{
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rte_bbdev_log_debug(
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"FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08"
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PRIx32, mmio_base, offset);
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rte_bbdev_log_debug(
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"RING_BASE_ADDR = 0x%016"PRIx64,
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fpga_reg_read_64(mmio_base, offset));
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rte_bbdev_log_debug(
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"RING_HEAD_ADDR = 0x%016"PRIx64,
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fpga_reg_read_64(mmio_base, offset +
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FPGA_5GNR_FEC_RING_HEAD_ADDR));
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rte_bbdev_log_debug(
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"RING_SIZE = 0x%04"PRIx16,
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fpga_reg_read_16(mmio_base, offset +
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FPGA_5GNR_FEC_RING_SIZE));
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rte_bbdev_log_debug(
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"RING_MISC = 0x%02"PRIx8,
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fpga_reg_read_8(mmio_base, offset +
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FPGA_5GNR_FEC_RING_MISC));
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rte_bbdev_log_debug(
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"RING_ENABLE = 0x%02"PRIx8,
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fpga_reg_read_8(mmio_base, offset +
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FPGA_5GNR_FEC_RING_ENABLE));
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rte_bbdev_log_debug(
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"RING_FLUSH_QUEUE_EN = 0x%02"PRIx8,
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fpga_reg_read_8(mmio_base, offset +
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FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN));
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rte_bbdev_log_debug(
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"RING_SHADOW_TAIL = 0x%04"PRIx16,
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fpga_reg_read_16(mmio_base, offset +
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FPGA_5GNR_FEC_RING_SHADOW_TAIL));
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rte_bbdev_log_debug(
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"RING_HEAD_POINT = 0x%04"PRIx16,
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fpga_reg_read_16(mmio_base, offset +
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FPGA_5GNR_FEC_RING_HEAD_POINT));
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}
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/* Read Static Register of FPGA 5GNR FEC device */
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static inline void
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print_static_reg_debug_info(void *mmio_base)
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{
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uint16_t config = fpga_reg_read_16(mmio_base,
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FPGA_5GNR_FEC_CONFIGURATION);
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uint8_t qmap_done = fpga_reg_read_8(mmio_base,
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FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE);
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uint16_t lb_factor = fpga_reg_read_16(mmio_base,
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FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR);
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uint16_t ring_desc_len = fpga_reg_read_16(mmio_base,
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FPGA_5GNR_FEC_RING_DESC_LEN);
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uint16_t flr_time_out = fpga_reg_read_16(mmio_base,
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FPGA_5GNR_FEC_FLR_TIME_OUT);
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rte_bbdev_log_debug("UL.DL Weights = %u.%u",
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((uint8_t)config), ((uint8_t)(config >> 8)));
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rte_bbdev_log_debug("UL.DL Load Balance = %u.%u",
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((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8)));
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rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s",
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(qmap_done > 0) ? "READY" : "NOT-READY");
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rte_bbdev_log_debug("Ring Descriptor Size = %u bytes",
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ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES);
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rte_bbdev_log_debug("FLR Timeout = %f usec",
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(float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT);
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}
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/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */
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static void
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print_dma_dec_desc_debug_info(union fpga_dma_desc *desc)
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{
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rte_bbdev_log_debug("DMA response desc %p\n"
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"\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")"
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" | crcb_pass (%"PRIu32") | error(%"PRIu32")\n"
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"\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | "
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"bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n"
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"\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") "
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"| irq_en(%"PRIu32")\n"
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"\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | "
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"drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n"
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"\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n"
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"\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n"
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"\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")"
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"| out_add (0x%08"PRIx32"%08"PRIx32")",
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desc,
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(uint32_t)desc->dec_req.done,
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(uint32_t)desc->dec_req.iter,
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(uint32_t)desc->dec_req.et_pass,
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(uint32_t)desc->dec_req.crcb_pass,
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(uint32_t)desc->dec_req.error,
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(uint32_t)desc->dec_req.qm_idx,
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(uint32_t)desc->dec_req.max_iter,
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(uint32_t)desc->dec_req.bg_idx,
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(uint32_t)desc->dec_req.harqin_en,
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(uint32_t)desc->dec_req.zc,
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(uint32_t)desc->dec_req.hbstroe_offset,
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(uint32_t)desc->dec_req.num_null,
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(uint32_t)desc->dec_req.irq_en,
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(uint32_t)desc->dec_req.ncb,
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(uint32_t)desc->dec_req.desc_idx,
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(uint32_t)desc->dec_req.drop_crc24b,
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(uint32_t)desc->dec_req.rv,
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(uint32_t)desc->dec_req.crc24b_ind,
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(uint32_t)desc->dec_req.et_dis,
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(uint32_t)desc->dec_req.harq_input_length,
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(uint32_t)desc->dec_req.rm_e,
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(uint32_t)desc->dec_req.cbs_in_op,
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(uint32_t)desc->dec_req.in_addr_hi,
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(uint32_t)desc->dec_req.in_addr_lw,
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(uint32_t)desc->dec_req.out_addr_hi,
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(uint32_t)desc->dec_req.out_addr_lw);
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uint32_t *word = (uint32_t *) desc;
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rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
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"%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
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word[0], word[1], word[2], word[3],
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word[4], word[5], word[6], word[7]);
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}
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/* Print decode DMA Descriptor of FPGA 5GNR encoder device */
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static void
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print_dma_enc_desc_debug_info(union fpga_dma_desc *desc)
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{
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rte_bbdev_log_debug("DMA response desc %p\n"
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"%"PRIu32" %"PRIu32"\n"
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"K' %"PRIu32" E %"PRIu32" desc %"PRIu32" Z %"PRIu32"\n"
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"BG %"PRIu32" Qm %"PRIu32" CRC %"PRIu32" IRQ %"PRIu32"\n"
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"k0 %"PRIu32" Ncb %"PRIu32" F %"PRIu32"\n",
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desc,
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(uint32_t)desc->enc_req.done,
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(uint32_t)desc->enc_req.error,
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(uint32_t)desc->enc_req.k_,
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(uint32_t)desc->enc_req.rm_e,
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(uint32_t)desc->enc_req.desc_idx,
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(uint32_t)desc->enc_req.zc,
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(uint32_t)desc->enc_req.bg_idx,
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(uint32_t)desc->enc_req.qm_idx,
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(uint32_t)desc->enc_req.crc_en,
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(uint32_t)desc->enc_req.irq_en,
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(uint32_t)desc->enc_req.k0,
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(uint32_t)desc->enc_req.ncb,
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(uint32_t)desc->enc_req.num_null);
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uint32_t *word = (uint32_t *) desc;
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rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n"
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"%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n",
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word[0], word[1], word[2], word[3],
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word[4], word[5], word[6], word[7]);
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}
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#endif
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static int
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fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
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{
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@ -360,6 +515,10 @@ fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
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rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]",
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queue_id, q_idx);
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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/* Read FPGA Ring Control Registers after configuration*/
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print_ring_reg_debug_info(d->mmio_base, ring_offset);
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#endif
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return 0;
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}
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@ -484,6 +643,7 @@ static const struct rte_bbdev_ops fpga_ops = {
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.queue_start = fpga_queue_start,
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.queue_release = fpga_queue_release,
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};
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static inline void
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fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc,
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struct rte_bbdev_stats *queue_stats)
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@ -728,6 +888,96 @@ fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op,
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return 0;
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}
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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/* Validates LDPC encoder parameters */
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static int
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validate_enc_op(struct rte_bbdev_enc_op *op __rte_unused)
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{
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struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc;
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struct rte_bbdev_op_enc_ldpc_cb_params *cb = NULL;
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struct rte_bbdev_op_enc_ldpc_tb_params *tb = NULL;
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if (ldpc_enc->input.length >
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RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) {
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rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d",
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ldpc_enc->input.length,
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RTE_BBDEV_LDPC_MAX_CB_SIZE);
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return -1;
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}
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if (op->mempool == NULL) {
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rte_bbdev_log(ERR, "Invalid mempool pointer");
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return -1;
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}
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if (ldpc_enc->input.data == NULL) {
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rte_bbdev_log(ERR, "Invalid input pointer");
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return -1;
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}
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if (ldpc_enc->output.data == NULL) {
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rte_bbdev_log(ERR, "Invalid output pointer");
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return -1;
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}
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if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) {
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rte_bbdev_log(ERR,
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"basegraph (%u) is out of range 1 <= value <= 2",
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ldpc_enc->basegraph);
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return -1;
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}
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if (ldpc_enc->code_block_mode > 1) {
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rte_bbdev_log(ERR,
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"code_block_mode (%u) is out of range 0:Tb 1:CB",
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ldpc_enc->code_block_mode);
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return -1;
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}
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if (ldpc_enc->code_block_mode == 0) {
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tb = &ldpc_enc->tb_params;
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if (tb->c == 0) {
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rte_bbdev_log(ERR,
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"c (%u) is out of range 1 <= value <= %u",
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tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
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return -1;
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}
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if (tb->cab > tb->c) {
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rte_bbdev_log(ERR,
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"cab (%u) is greater than c (%u)",
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tb->cab, tb->c);
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return -1;
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}
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if ((tb->ea < RTE_BBDEV_LDPC_MIN_CB_SIZE)
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&& tb->r < tb->cab) {
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rte_bbdev_log(ERR,
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"ea (%u) is less than %u or it is not even",
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tb->ea, RTE_BBDEV_LDPC_MIN_CB_SIZE);
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return -1;
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}
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if ((tb->eb < RTE_BBDEV_LDPC_MIN_CB_SIZE)
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&& tb->c > tb->cab) {
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rte_bbdev_log(ERR,
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"eb (%u) is less than %u",
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tb->eb, RTE_BBDEV_LDPC_MIN_CB_SIZE);
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return -1;
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}
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if (tb->r > (tb->c - 1)) {
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rte_bbdev_log(ERR,
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"r (%u) is greater than c - 1 (%u)",
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tb->r, tb->c - 1);
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return -1;
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}
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} else {
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cb = &ldpc_enc->cb_params;
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if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
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rte_bbdev_log(ERR,
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"e (%u) is less than %u or it is not even",
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cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE);
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return -1;
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}
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}
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return 0;
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}
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#endif
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static inline char *
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mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
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{
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@ -740,6 +990,69 @@ mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len)
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return tail;
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}
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#ifdef RTE_LIBRTE_BBDEV_DEBUG
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/* Validates LDPC decoder parameters */
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static int
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validate_dec_op(struct rte_bbdev_dec_op *op __rte_unused)
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{
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struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec;
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struct rte_bbdev_op_dec_ldpc_cb_params *cb = NULL;
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struct rte_bbdev_op_dec_ldpc_tb_params *tb = NULL;
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if (op->mempool == NULL) {
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rte_bbdev_log(ERR, "Invalid mempool pointer");
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return -1;
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}
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if (ldpc_dec->rv_index > 3) {
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rte_bbdev_log(ERR,
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"rv_index (%u) is out of range 0 <= value <= 3",
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ldpc_dec->rv_index);
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return -1;
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}
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if (ldpc_dec->iter_max == 0) {
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rte_bbdev_log(ERR,
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"iter_max (%u) is equal to 0",
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ldpc_dec->iter_max);
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return -1;
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}
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if (ldpc_dec->code_block_mode > 1) {
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rte_bbdev_log(ERR,
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"code_block_mode (%u) is out of range 0 <= value <= 1",
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ldpc_dec->code_block_mode);
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return -1;
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}
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if (ldpc_dec->code_block_mode == 0) {
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tb = &ldpc_dec->tb_params;
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if (tb->c < 1) {
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rte_bbdev_log(ERR,
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"c (%u) is out of range 1 <= value <= %u",
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tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS);
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return -1;
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}
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if (tb->cab > tb->c) {
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rte_bbdev_log(ERR,
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"cab (%u) is greater than c (%u)",
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tb->cab, tb->c);
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return -1;
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}
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} else {
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cb = &ldpc_dec->cb_params;
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if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) {
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rte_bbdev_log(ERR,
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"e (%u) is out of range %u <= value <= %u",
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cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE,
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RTE_BBDEV_LDPC_MAX_CB_SIZE);
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return -1;
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}
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}
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return 0;
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}
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||||
#endif
|
||||
|
||||
static inline int
|
||||
enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
|
||||
uint16_t desc_offset)
|
||||
@ -758,6 +1071,15 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
|
||||
uint16_t ring_offset;
|
||||
uint16_t K, k_;
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
/* Validate op structure */
|
||||
/* FIXME */
|
||||
if (validate_enc_op(op) == -1) {
|
||||
rte_bbdev_log(ERR, "LDPC encoder validation failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear op status */
|
||||
op->status = 0;
|
||||
|
||||
@ -819,6 +1141,9 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op,
|
||||
return -1;
|
||||
}
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
print_dma_enc_desc_debug_info(desc);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -841,6 +1166,14 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
|
||||
uint16_t out_offset = dec->hard_output.offset;
|
||||
uint32_t harq_offset = 0;
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
/* Validate op structure */
|
||||
if (validate_dec_op(op) == -1) {
|
||||
rte_bbdev_log(ERR, "LDPC decoder validation failed");
|
||||
return -EINVAL;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear op status */
|
||||
op->status = 0;
|
||||
|
||||
@ -912,6 +1245,10 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op,
|
||||
return -1;
|
||||
}
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
print_dma_dec_desc_debug_info(desc);
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -1048,6 +1385,10 @@ dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q,
|
||||
|
||||
rte_bbdev_log_debug("DMA response desc %p", desc);
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
print_dma_enc_desc_debug_info(desc);
|
||||
#endif
|
||||
|
||||
*op = desc->enc_req.op_addr;
|
||||
/* Check the descriptor error field, return 1 on error */
|
||||
desc_error = check_desc_error(desc->enc_req.error);
|
||||
@ -1074,6 +1415,10 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op,
|
||||
/* make sure the response is read atomically */
|
||||
rte_smp_rmb();
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
print_dma_dec_desc_debug_info(desc);
|
||||
#endif
|
||||
|
||||
*op = desc->dec_req.op_addr;
|
||||
|
||||
if (check_bit((*op)->ldpc_dec.op_flags,
|
||||
@ -1229,6 +1574,17 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv,
|
||||
rte_bbdev_log_debug("bbdev id = %u [%s]",
|
||||
bbdev->data->dev_id, dev_name);
|
||||
|
||||
struct fpga_5gnr_fec_device *d = bbdev->data->dev_private;
|
||||
uint32_t version_id = fpga_reg_read_32(d->mmio_base,
|
||||
FPGA_5GNR_FEC_VERSION_ID);
|
||||
rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u",
|
||||
((uint16_t)(version_id >> 16)), ((uint16_t)version_id));
|
||||
|
||||
#ifdef RTE_LIBRTE_BBDEV_DEBUG
|
||||
if (!strcmp(bbdev->device->driver->name,
|
||||
RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME)))
|
||||
print_static_reg_debug_info(d->mmio_base);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user