net/hns3: add some definitions for data structure and macro
This patch adds some data structure definitions, macro definitions and inline functions for hns3 PMD drivers. Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com> Signed-off-by: Chunsong Feng <fengchunsong@huawei.com> Signed-off-by: Min Hu (Connor) <humin29@huawei.com> Signed-off-by: Hao Chen <chenhao164@huawei.com> Signed-off-by: Huisong Li <lihuisong@huawei.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Wei Hu (Xavier)
Ferruh Yigit
parent
4c7dfaad98
commit
1265b5372d
611
drivers/net/hns3/hns3_ethdev.h
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611
drivers/net/hns3/hns3_ethdev.h
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@ -0,0 +1,611 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018-2019 Hisilicon Limited.
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*/
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#ifndef _HNS3_ETHDEV_H_
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#define _HNS3_ETHDEV_H_
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#include <sys/time.h>
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#include <rte_alarm.h>
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/* Vendor ID */
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#define PCI_VENDOR_ID_HUAWEI 0x19e5
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/* Device IDs */
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#define HNS3_DEV_ID_GE 0xA220
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#define HNS3_DEV_ID_25GE 0xA221
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#define HNS3_DEV_ID_25GE_RDMA 0xA222
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#define HNS3_DEV_ID_50GE_RDMA 0xA224
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#define HNS3_DEV_ID_100G_RDMA_MACSEC 0xA226
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#define HNS3_DEV_ID_100G_VF 0xA22E
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#define HNS3_DEV_ID_100G_RDMA_PFC_VF 0xA22F
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#define HNS3_UC_MACADDR_NUM 128
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#define HNS3_VF_UC_MACADDR_NUM 48
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#define HNS3_MC_MACADDR_NUM 128
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#define HNS3_MAX_BD_SIZE 65535
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#define HNS3_MAX_TX_BD_PER_PKT 8
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#define HNS3_MAX_FRAME_LEN 9728
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#define HNS3_MIN_FRAME_LEN 64
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#define HNS3_VLAN_TAG_SIZE 4
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#define HNS3_DEFAULT_RX_BUF_LEN 2048
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#define HNS3_ETH_OVERHEAD \
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(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + HNS3_VLAN_TAG_SIZE * 2)
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#define HNS3_PKTLEN_TO_MTU(pktlen) ((pktlen) - HNS3_ETH_OVERHEAD)
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#define HNS3_MAX_MTU (HNS3_MAX_FRAME_LEN - HNS3_ETH_OVERHEAD)
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#define HNS3_DEFAULT_MTU 1500UL
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#define HNS3_DEFAULT_FRAME_LEN (HNS3_DEFAULT_MTU + HNS3_ETH_OVERHEAD)
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#define HNS3_4_TCS 4
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#define HNS3_8_TCS 8
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#define HNS3_MAX_TC_NUM 8
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#define HNS3_MAX_PF_NUM 8
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#define HNS3_UMV_TBL_SIZE 3072
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#define HNS3_DEFAULT_UMV_SPACE_PER_PF \
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(HNS3_UMV_TBL_SIZE / HNS3_MAX_PF_NUM)
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#define HNS3_PF_CFG_BLOCK_SIZE 32
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#define HNS3_PF_CFG_DESC_NUM \
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(HNS3_PF_CFG_BLOCK_SIZE / HNS3_CFG_RD_LEN_BYTES)
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#define HNS3_DEFAULT_ENABLE_PFC_NUM 0
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#define HNS3_INTR_UNREG_FAIL_RETRY_CNT 5
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#define HNS3_INTR_UNREG_FAIL_DELAY_MS 500
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#define HNS3_QUIT_RESET_CNT 10
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#define HNS3_QUIT_RESET_DELAY_MS 100
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#define HNS3_POLL_RESPONE_MS 1
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#define HNS3_MAX_USER_PRIO 8
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#define HNS3_PG_NUM 4
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enum hns3_fc_mode {
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HNS3_FC_NONE,
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HNS3_FC_RX_PAUSE,
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HNS3_FC_TX_PAUSE,
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HNS3_FC_FULL,
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HNS3_FC_DEFAULT
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};
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#define HNS3_SCH_MODE_SP 0
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#define HNS3_SCH_MODE_DWRR 1
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struct hns3_pg_info {
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uint8_t pg_id;
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uint8_t pg_sch_mode; /* 0: sp; 1: dwrr */
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uint8_t tc_bit_map;
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uint32_t bw_limit;
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uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
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};
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struct hns3_tc_info {
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uint8_t tc_id;
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uint8_t tc_sch_mode; /* 0: sp; 1: dwrr */
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uint8_t pgid;
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uint32_t bw_limit;
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uint8_t up_to_tc_map; /* user priority maping on the TC */
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};
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struct hns3_dcb_info {
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uint8_t num_tc;
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uint8_t num_pg; /* It must be 1 if vNET-Base schd */
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uint8_t pg_dwrr[HNS3_PG_NUM];
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uint8_t prio_tc[HNS3_MAX_USER_PRIO];
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struct hns3_pg_info pg_info[HNS3_PG_NUM];
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struct hns3_tc_info tc_info[HNS3_MAX_TC_NUM];
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uint8_t hw_pfc_map; /* Allow for packet drop or not on this TC */
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uint8_t pfc_en; /* Pfc enabled or not for user priority */
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};
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enum hns3_fc_status {
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HNS3_FC_STATUS_NONE,
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HNS3_FC_STATUS_MAC_PAUSE,
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HNS3_FC_STATUS_PFC,
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};
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struct hns3_tc_queue_info {
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uint8_t tqp_offset; /* TQP offset from base TQP */
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uint8_t tqp_count; /* Total TQPs */
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uint8_t tc; /* TC index */
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bool enable; /* If this TC is enable or not */
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};
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struct hns3_cfg {
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uint8_t vmdq_vport_num;
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uint8_t tc_num;
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uint16_t tqp_desc_num;
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uint16_t rx_buf_len;
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uint16_t rss_size_max;
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uint8_t phy_addr;
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uint8_t media_type;
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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uint8_t default_speed;
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uint32_t numa_node_map;
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uint8_t speed_ability;
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uint16_t umv_space;
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};
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/* mac media type */
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enum hns3_media_type {
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HNS3_MEDIA_TYPE_UNKNOWN,
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HNS3_MEDIA_TYPE_FIBER,
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HNS3_MEDIA_TYPE_COPPER,
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HNS3_MEDIA_TYPE_BACKPLANE,
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HNS3_MEDIA_TYPE_NONE,
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};
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struct hns3_mac {
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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bool default_addr_setted; /* whether default addr(mac_addr) is setted */
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uint8_t media_type;
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uint8_t phy_addr;
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uint8_t link_duplex : 1; /* ETH_LINK_[HALF/FULL]_DUPLEX */
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uint8_t link_autoneg : 1; /* ETH_LINK_[AUTONEG/FIXED] */
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uint8_t link_status : 1; /* ETH_LINK_[DOWN/UP] */
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uint32_t link_speed; /* ETH_SPEED_NUM_ */
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};
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/* Primary process maintains driver state in main thread.
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*
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* +---------------+
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* | UNINITIALIZED |<-----------+
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* +---------------+ |
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* |.eth_dev_init |.eth_dev_uninit
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* V |
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* +---------------+------------+
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* | INITIALIZED |
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* +---------------+<-----------<---------------+
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* |.dev_configure | |
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* V |failed |
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* +---------------+------------+ |
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* | CONFIGURING | |
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* +---------------+----+ |
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* |success | |
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* | | +---------------+
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* | | | CLOSING |
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* | | +---------------+
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* | | ^
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* V |.dev_configure |
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* +---------------+----+ |.dev_close
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* | CONFIGURED |----------------------------+
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* +---------------+<-----------+
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* |.dev_start |
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* V |
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* +---------------+ |
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* | STARTING |------------^
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* +---------------+ failed |
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* |success |
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* | +---------------+
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* | | STOPPING |
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* | +---------------+
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* | ^
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* V |.dev_stop
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* +---------------+------------+
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* | STARTED |
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* +---------------+
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*/
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enum hns3_adapter_state {
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HNS3_NIC_UNINITIALIZED = 0,
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HNS3_NIC_INITIALIZED,
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HNS3_NIC_CONFIGURING,
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HNS3_NIC_CONFIGURED,
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HNS3_NIC_STARTING,
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HNS3_NIC_STARTED,
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HNS3_NIC_STOPPING,
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HNS3_NIC_CLOSING,
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HNS3_NIC_CLOSED,
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HNS3_NIC_REMOVED,
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HNS3_NIC_NSTATES
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};
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/* Reset various stages, execute in order */
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enum hns3_reset_stage {
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/* Stop query services, stop transceiver, disable MAC */
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RESET_STAGE_DOWN,
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/* Clear reset completion flags, disable send command */
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RESET_STAGE_PREWAIT,
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/* Inform IMP to start resetting */
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RESET_STAGE_REQ_HW_RESET,
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/* Waiting for hardware reset to complete */
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RESET_STAGE_WAIT,
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/* Reinitialize hardware */
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RESET_STAGE_DEV_INIT,
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/* Restore user settings and enable MAC */
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RESET_STAGE_RESTORE,
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/* Restart query services, start transceiver */
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RESET_STAGE_DONE,
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/* Not in reset state */
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RESET_STAGE_NONE,
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};
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enum hns3_reset_level {
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HNS3_NONE_RESET,
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HNS3_VF_FUNC_RESET, /* A VF function reset */
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/*
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* All VFs under a PF perform function reset.
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* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
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* of the reset level and the one defined in kernel driver should be
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* same.
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*/
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HNS3_VF_PF_FUNC_RESET = 2,
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/*
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* All VFs under a PF perform FLR reset.
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* Kernel PF driver use mailbox to inform DPDK VF to do reset, the value
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* of the reset level and the one defined in kernel driver should be
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* same.
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*/
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HNS3_VF_FULL_RESET = 3,
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HNS3_FLR_RESET, /* A VF perform FLR reset */
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/* All VFs under the rootport perform a global or IMP reset */
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HNS3_VF_RESET,
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HNS3_FUNC_RESET, /* A PF function reset */
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/* All PFs under the rootport perform a global reset */
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HNS3_GLOBAL_RESET,
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HNS3_IMP_RESET, /* All PFs under the rootport perform a IMP reset */
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HNS3_MAX_RESET
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};
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enum hns3_wait_result {
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HNS3_WAIT_UNKNOWN,
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HNS3_WAIT_REQUEST,
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HNS3_WAIT_SUCCESS,
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HNS3_WAIT_TIMEOUT
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};
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#define HNS3_RESET_SYNC_US 100000
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struct hns3_reset_stats {
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uint64_t request_cnt; /* Total request reset times */
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uint64_t global_cnt; /* Total GLOBAL reset times */
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uint64_t imp_cnt; /* Total IMP reset times */
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uint64_t exec_cnt; /* Total reset executive times */
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uint64_t success_cnt; /* Total reset successful times */
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uint64_t fail_cnt; /* Total reset failed times */
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uint64_t merge_cnt; /* Total merged in high reset times */
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};
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struct hns3_hw;
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struct hns3_adapter;
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typedef bool (*check_completion_func)(struct hns3_hw *hw);
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struct hns3_wait_data {
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void *hns;
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uint64_t end_ms;
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uint64_t interval;
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int16_t count;
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enum hns3_wait_result result;
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check_completion_func check_completion;
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};
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struct hns3_reset_ops {
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void (*reset_service)(void *arg);
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int (*stop_service)(struct hns3_adapter *hns);
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int (*prepare_reset)(struct hns3_adapter *hns);
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int (*wait_hardware_ready)(struct hns3_adapter *hns);
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int (*reinit_dev)(struct hns3_adapter *hns);
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int (*restore_conf)(struct hns3_adapter *hns);
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int (*start_service)(struct hns3_adapter *hns);
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};
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enum hns3_schedule {
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SCHEDULE_NONE,
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SCHEDULE_PENDING,
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SCHEDULE_REQUESTED,
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SCHEDULE_DEFERRED,
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};
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struct hns3_reset_data {
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enum hns3_reset_stage stage;
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rte_atomic16_t schedule;
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/* Reset flag, covering the entire reset process */
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rte_atomic16_t resetting;
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/* Used to disable sending cmds during reset */
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rte_atomic16_t disable_cmd;
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/* The reset level being processed */
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enum hns3_reset_level level;
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/* Reset level set, each bit represents a reset level */
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uint64_t pending;
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/* Request reset level set, from interrupt or mailbox */
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uint64_t request;
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int attempts; /* Reset failure retry */
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int retries; /* Timeout failure retry in reset_post */
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/*
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* At the time of global or IMP reset, the command cannot be sent to
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* stop the tx/rx queues. Tx/Rx queues may be access mbuf during the
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* reset process, so the mbuf is required to be released after the reset
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* is completed.The mbuf_deferred_free is used to mark whether mbuf
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* needs to be released.
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*/
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bool mbuf_deferred_free;
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struct timeval start_time;
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struct hns3_reset_stats stats;
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const struct hns3_reset_ops *ops;
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struct hns3_wait_data *wait_data;
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};
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struct hns3_hw {
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struct rte_eth_dev_data *data;
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void *io_base;
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struct hns3_mac mac;
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unsigned int secondary_cnt; /* Number of secondary processes init'd. */
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uint32_t fw_version;
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uint16_t num_msi;
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uint16_t total_tqps_num; /* total task queue pairs of this PF */
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uint16_t tqps_num; /* num task queue pairs of this function */
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uint16_t rss_size_max; /* HW defined max RSS task queue */
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uint16_t rx_buf_len;
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uint16_t num_tx_desc; /* desc num of per tx queue */
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uint16_t num_rx_desc; /* desc num of per rx queue */
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struct rte_ether_addr mc_addrs[HNS3_MC_MACADDR_NUM];
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int mc_addrs_num; /* Multicast mac addresses number */
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uint8_t num_tc; /* Total number of enabled TCs */
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uint8_t hw_tc_map;
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enum hns3_fc_mode current_mode;
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enum hns3_fc_mode requested_mode;
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struct hns3_dcb_info dcb_info;
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enum hns3_fc_status current_fc_status; /* current flow control status */
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struct hns3_tc_queue_info tc_queue[HNS3_MAX_TC_NUM];
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uint16_t alloc_tqps;
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uint16_t alloc_rss_size; /* Queue number per TC */
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uint32_t flag;
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/*
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* PMD setup and configuration is not thread safe. Since it is not
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* performance sensitive, it is better to guarantee thread-safety
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* and add device level lock. Adapter control operations which
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* change its state should acquire the lock.
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*/
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rte_spinlock_t lock;
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enum hns3_adapter_state adapter_state;
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struct hns3_reset_data reset;
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};
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#define HNS3_FLAG_TC_BASE_SCH_MODE 1
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#define HNS3_FLAG_VNET_BASE_SCH_MODE 2
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struct hns3_err_msix_intr_stats {
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uint64_t mac_afifo_tnl_intr_cnt;
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uint64_t ppu_mpf_abnormal_intr_st2_cnt;
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uint64_t ssu_port_based_pf_intr_cnt;
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uint64_t ppp_pf_abnormal_intr_cnt;
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uint64_t ppu_pf_abnormal_intr_cnt;
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};
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/* vlan entry information. */
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struct hns3_user_vlan_table {
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LIST_ENTRY(hns3_user_vlan_table) next;
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bool hd_tbl_status;
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uint16_t vlan_id;
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};
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struct hns3_port_base_vlan_config {
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uint16_t state;
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uint16_t pvid;
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};
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/* Vlan tag configuration for RX direction */
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struct hns3_rx_vtag_cfg {
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uint8_t rx_vlan_offload_en; /* Whether enable rx vlan offload */
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uint8_t strip_tag1_en; /* Whether strip inner vlan tag */
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uint8_t strip_tag2_en; /* Whether strip outer vlan tag */
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uint8_t vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
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uint8_t vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
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};
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/* Vlan tag configuration for TX direction */
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struct hns3_tx_vtag_cfg {
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bool accept_tag1; /* Whether accept tag1 packet from host */
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bool accept_untag1; /* Whether accept untag1 packet from host */
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bool accept_tag2;
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bool accept_untag2;
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bool insert_tag1_en; /* Whether insert inner vlan tag */
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bool insert_tag2_en; /* Whether insert outer vlan tag */
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uint16_t default_tag1; /* The default inner vlan tag to insert */
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uint16_t default_tag2; /* The default outer vlan tag to insert */
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};
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struct hns3_vtag_cfg {
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struct hns3_rx_vtag_cfg rx_vcfg;
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struct hns3_tx_vtag_cfg tx_vcfg;
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};
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/* Request types for IPC. */
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enum hns3_mp_req_type {
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HNS3_MP_REQ_START_RXTX = 1,
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HNS3_MP_REQ_STOP_RXTX,
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HNS3_MP_REQ_MAX
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};
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||||
/* Pameters for IPC. */
|
||||
struct hns3_mp_param {
|
||||
enum hns3_mp_req_type type;
|
||||
int port_id;
|
||||
int result;
|
||||
};
|
||||
|
||||
/* Request timeout for IPC. */
|
||||
#define HNS3_MP_REQ_TIMEOUT_SEC 5
|
||||
|
||||
/* Key string for IPC. */
|
||||
#define HNS3_MP_NAME "net_hns3_mp"
|
||||
|
||||
struct hns3_pf {
|
||||
struct hns3_adapter *adapter;
|
||||
bool is_main_pf;
|
||||
|
||||
uint32_t pkt_buf_size; /* Total pf buf size for tx/rx */
|
||||
uint32_t tx_buf_size; /* Tx buffer size for each TC */
|
||||
uint32_t dv_buf_size; /* Dv buffer size for each TC */
|
||||
|
||||
uint16_t mps; /* Max packet size */
|
||||
|
||||
uint8_t tx_sch_mode;
|
||||
uint8_t tc_max; /* max number of tc driver supported */
|
||||
uint8_t local_max_tc; /* max number of local tc */
|
||||
uint8_t pfc_max;
|
||||
uint8_t prio_tc[HNS3_MAX_USER_PRIO]; /* TC indexed by prio */
|
||||
uint16_t pause_time;
|
||||
bool support_fc_autoneg; /* support FC autonegotiate */
|
||||
|
||||
uint16_t wanted_umv_size;
|
||||
uint16_t max_umv_size;
|
||||
uint16_t used_umv_size;
|
||||
|
||||
/* Statistics information for abnormal interrupt */
|
||||
struct hns3_err_msix_intr_stats abn_int_stats;
|
||||
|
||||
bool support_sfp_query;
|
||||
|
||||
struct hns3_vtag_cfg vtag_config;
|
||||
struct hns3_port_base_vlan_config port_base_vlan_cfg;
|
||||
LIST_HEAD(vlan_tbl, hns3_user_vlan_table) vlan_list;
|
||||
};
|
||||
|
||||
struct hns3_vf {
|
||||
struct hns3_adapter *adapter;
|
||||
};
|
||||
|
||||
struct hns3_adapter {
|
||||
struct hns3_hw hw;
|
||||
|
||||
/* Specific for PF or VF */
|
||||
bool is_vf; /* false - PF, true - VF */
|
||||
union {
|
||||
struct hns3_pf pf;
|
||||
struct hns3_vf vf;
|
||||
};
|
||||
};
|
||||
|
||||
#define HNS3_DEV_SUPPORT_DCB_B 0x0
|
||||
|
||||
#define hns3_dev_dcb_supported(hw) \
|
||||
hns3_get_bit((hw)->flag, HNS3_DEV_SUPPORT_DCB_B)
|
||||
|
||||
#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
|
||||
(&((struct hns3_adapter *)adapter)->hw)
|
||||
#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
|
||||
((struct hns3_adapter *)adapter)
|
||||
#define HNS3_DEV_PRIVATE_TO_PF(adapter) \
|
||||
(&((struct hns3_adapter *)adapter)->pf)
|
||||
#define HNS3VF_DEV_PRIVATE_TO_VF(adapter) \
|
||||
(&((struct hns3_adapter *)adapter)->vf)
|
||||
#define HNS3_DEV_HW_TO_ADAPTER(hw) \
|
||||
container_of(hw, struct hns3_adapter, hw)
|
||||
|
||||
#define hns3_set_field(origin, mask, shift, val) \
|
||||
do { \
|
||||
(origin) &= (~(mask)); \
|
||||
(origin) |= ((val) << (shift)) & (mask); \
|
||||
} while (0)
|
||||
#define hns3_get_field(origin, mask, shift) \
|
||||
(((origin) & (mask)) >> (shift))
|
||||
#define hns3_set_bit(origin, shift, val) \
|
||||
hns3_set_field((origin), (0x1UL << (shift)), (shift), (val))
|
||||
#define hns3_get_bit(origin, shift) \
|
||||
hns3_get_field((origin), (0x1UL << (shift)), (shift))
|
||||
|
||||
/*
|
||||
* upper_32_bits - return bits 32-63 of a number
|
||||
* A basic shift-right of a 64- or 32-bit quantity. Use this to suppress
|
||||
* the "right shift count >= width of type" warning when that quantity is
|
||||
* 32-bits.
|
||||
*/
|
||||
#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16))
|
||||
|
||||
/* lower_32_bits - return bits 0-31 of a number */
|
||||
#define lower_32_bits(n) ((uint32_t)(n))
|
||||
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
|
||||
#define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
|
||||
#define GENMASK(h, l) \
|
||||
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
|
||||
|
||||
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
|
||||
#define rounddown(x, y) ((x) - ((x) % (y)))
|
||||
|
||||
#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
|
||||
|
||||
#define max_t(type, x, y) ({ \
|
||||
type __max1 = (x); \
|
||||
type __max2 = (y); \
|
||||
__max1 > __max2 ? __max1 : __max2; })
|
||||
|
||||
static inline void hns3_write_reg(void *base, uint32_t reg, uint32_t value)
|
||||
{
|
||||
rte_write32(value, (volatile void *)((char *)base + reg));
|
||||
}
|
||||
|
||||
static inline uint32_t hns3_read_reg(void *base, uint32_t reg)
|
||||
{
|
||||
return rte_read32((volatile void *)((char *)base + reg));
|
||||
}
|
||||
|
||||
#define hns3_write_dev(a, reg, value) \
|
||||
hns3_write_reg((a)->io_base, (reg), (value))
|
||||
|
||||
#define hns3_read_dev(a, reg) \
|
||||
hns3_read_reg((a)->io_base, (reg))
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
#define NEXT_ITEM_OF_ACTION(act, actions, index) \
|
||||
do { \
|
||||
act = (actions) + (index); \
|
||||
while (act->type == RTE_FLOW_ACTION_TYPE_VOID) { \
|
||||
(index)++; \
|
||||
act = actions + index; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define MSEC_PER_SEC 1000L
|
||||
#define USEC_PER_MSEC 1000L
|
||||
|
||||
static inline uint64_t
|
||||
get_timeofday_ms(void)
|
||||
{
|
||||
struct timeval tv;
|
||||
|
||||
(void)gettimeofday(&tv, NULL);
|
||||
|
||||
return (uint64_t)tv.tv_sec * MSEC_PER_SEC + tv.tv_usec / USEC_PER_MSEC;
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
hns3_atomic_test_bit(unsigned int nr, volatile uint64_t *addr)
|
||||
{
|
||||
uint64_t res;
|
||||
|
||||
res = (__atomic_load_n(addr, __ATOMIC_RELAXED) & (1UL << nr)) != 0;
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline void
|
||||
hns3_atomic_set_bit(unsigned int nr, volatile uint64_t *addr)
|
||||
{
|
||||
__atomic_fetch_or(addr, (1UL << nr), __ATOMIC_RELAXED);
|
||||
}
|
||||
|
||||
static inline void
|
||||
hns3_atomic_clear_bit(unsigned int nr, volatile uint64_t *addr)
|
||||
{
|
||||
__atomic_fetch_and(addr, ~(1UL << nr), __ATOMIC_RELAXED);
|
||||
}
|
||||
|
||||
static inline int64_t
|
||||
hns3_test_and_clear_bit(unsigned int nr, volatile uint64_t *addr)
|
||||
{
|
||||
uint64_t mask = (1UL << nr);
|
||||
|
||||
return __atomic_fetch_and(addr, ~mask, __ATOMIC_RELAXED) & mask;
|
||||
}
|
||||
|
||||
#endif /* _HNS3_ETHDEV_H_ */
|
||||
Loading…
Reference in New Issue
Block a user