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common/cnxk: fix shift offset for TL3 length disable

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Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE
register to be 24 instead of zero similar to other level SHAPE
registers. Also mask unused bits in adjust value.

Fixes: 0885429c30 ("common/cnxk: add NIX TM hierarchy enable/disable")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
This commit is contained in:
Nithin Dabilpuram 2022-01-21 17:34:15 +05:30 committed by Jerin Jacob
parent 474e275b1b
commit 132dac7536
1 changed files with 2 additions and 1 deletions
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3
drivers/common/cnxk/roc_nix_tm_utils.c
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@ -642,6 +642,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node,
else if (profile)
adjust = profile->pkt_len_adj;
adjust &= 0x1FF;
plt_tm_dbg("Shaper config node %s(%u) lvl %u id %u, "
"pir %" PRIu64 "(%" PRIu64 "B),"
" cir %" PRIu64 "(%" PRIu64 "B)"
@ -708,7 +709,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node,
/* Configure RED algo */
reg[k] = NIX_AF_TL3X_SHAPE(schq);
regval[k] = (adjust | (uint64_t)node->red_algo << 9 |
(uint64_t)node->pkt_mode);
(uint64_t)node->pkt_mode << 24);
k++;
break;