dma/ioat: create dmadev instances on PCI probe
When a suitable device is found during the PCI probe, create a dmadev instance for each channel. Internal structures and HW definitions required for device creation are also included. Signed-off-by: Conor Walsh <conor.walsh@intel.com> Reviewed-by: Kevin Laatz <kevin.laatz@intel.com>
This commit is contained in:
Conor Walsh
Thomas Monjalon
parent
866e46bcd8
commit
13859ab773
@ -4,6 +4,7 @@
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#include <rte_bus_pci.h>
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#include <rte_dmadev_pmd.h>
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#include <rte_malloc.h>
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#include "ioat_internal.h"
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@ -14,6 +15,106 @@ RTE_LOG_REGISTER_DEFAULT(ioat_pmd_logtype, INFO);
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#define IOAT_PMD_NAME dmadev_ioat
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#define IOAT_PMD_NAME_STR RTE_STR(IOAT_PMD_NAME)
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/* Create a DMA device. */
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static int
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ioat_dmadev_create(const char *name, struct rte_pci_device *dev)
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{
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static const struct rte_dma_dev_ops ioat_dmadev_ops = { };
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struct rte_dma_dev *dmadev = NULL;
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struct ioat_dmadev *ioat = NULL;
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int retry = 0;
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if (!name) {
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IOAT_PMD_ERR("Invalid name of the device!");
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return -EINVAL;
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}
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/* Allocate device structure. */
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dmadev = rte_dma_pmd_allocate(name, dev->device.numa_node, sizeof(struct ioat_dmadev));
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if (dmadev == NULL) {
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IOAT_PMD_ERR("Unable to allocate dma device");
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return -ENOMEM;
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}
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dmadev->device = &dev->device;
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dmadev->fp_obj->dev_private = dmadev->data->dev_private;
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dmadev->dev_ops = &ioat_dmadev_ops;
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ioat = dmadev->data->dev_private;
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ioat->dmadev = dmadev;
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ioat->regs = dev->mem_resource[0].addr;
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ioat->doorbell = &ioat->regs->dmacount;
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ioat->qcfg.nb_desc = 0;
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ioat->desc_ring = NULL;
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ioat->version = ioat->regs->cbver;
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/* Do device initialization - reset and set error behaviour. */
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if (ioat->regs->chancnt != 1)
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IOAT_PMD_WARN("%s: Channel count == %d\n", __func__,
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ioat->regs->chancnt);
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/* Locked by someone else. */
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if (ioat->regs->chanctrl & IOAT_CHANCTRL_CHANNEL_IN_USE) {
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IOAT_PMD_WARN("%s: Channel appears locked\n", __func__);
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ioat->regs->chanctrl = 0;
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}
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/* clear any previous errors */
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if (ioat->regs->chanerr != 0) {
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uint32_t val = ioat->regs->chanerr;
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ioat->regs->chanerr = val;
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}
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ioat->regs->chancmd = IOAT_CHANCMD_SUSPEND;
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rte_delay_ms(1);
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ioat->regs->chancmd = IOAT_CHANCMD_RESET;
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rte_delay_ms(1);
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while (ioat->regs->chancmd & IOAT_CHANCMD_RESET) {
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ioat->regs->chainaddr = 0;
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rte_delay_ms(1);
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if (++retry >= 200) {
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IOAT_PMD_ERR("%s: cannot reset device. CHANCMD=%#"PRIx8
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", CHANSTS=%#"PRIx64", CHANERR=%#"PRIx32"\n",
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__func__,
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ioat->regs->chancmd,
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ioat->regs->chansts,
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ioat->regs->chanerr);
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rte_dma_pmd_release(name);
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return -EIO;
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}
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}
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ioat->regs->chanctrl = IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
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IOAT_CHANCTRL_ERR_COMPLETION_EN;
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dmadev->fp_obj->dev_private = ioat;
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dmadev->state = RTE_DMA_DEV_READY;
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return 0;
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}
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/* Destroy a DMA device. */
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static int
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ioat_dmadev_destroy(const char *name)
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{
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int ret;
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if (!name) {
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IOAT_PMD_ERR("Invalid device name");
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return -EINVAL;
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}
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ret = rte_dma_pmd_release(name);
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if (ret)
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IOAT_PMD_DEBUG("Device cleanup failed");
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return 0;
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}
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/* Probe DMA device. */
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static int
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ioat_dmadev_probe(struct rte_pci_driver *drv, struct rte_pci_device *dev)
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@ -24,7 +125,7 @@ ioat_dmadev_probe(struct rte_pci_driver *drv, struct rte_pci_device *dev)
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IOAT_PMD_INFO("Init %s on NUMA node %d", name, dev->device.numa_node);
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dev->device.driver = &drv->driver;
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return 0;
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return ioat_dmadev_create(name, dev);
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}
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/* Remove DMA device. */
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@ -38,7 +139,7 @@ ioat_dmadev_remove(struct rte_pci_device *dev)
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IOAT_PMD_INFO("Closing %s on NUMA node %d",
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name, dev->device.numa_node);
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return 0;
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return ioat_dmadev_destroy(name);
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}
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static const struct rte_pci_id pci_id_ioat_map[] = {
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@ -11,6 +11,8 @@ extern "C" {
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#include <stdint.h>
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#define IOAT_PCI_CHANERR_INT_OFFSET 0x180
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#define IOAT_VER_3_0 0x30
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#define IOAT_VER_3_3 0x33
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@ -28,6 +30,49 @@ extern "C" {
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#define IOAT_DEVICE_ID_BDXF 0x6f2F
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#define IOAT_DEVICE_ID_ICX 0x0b00
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#define IOAT_COMP_UPDATE_SHIFT 3
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#define IOAT_CMD_OP_SHIFT 24
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/* DMA Channel Registers */
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#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
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#define IOAT_CHANCTRL_COMPL_DCA_EN 0x0200
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#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
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#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
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#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
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#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
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#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
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#define IOAT_CHANCTRL_INT_REARM 0x0001
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struct ioat_registers {
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uint8_t chancnt;
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uint8_t xfercap;
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uint8_t genctrl;
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uint8_t intrctrl;
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uint32_t attnstatus;
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uint8_t cbver; /* 0x08 */
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uint8_t reserved4[0x3]; /* 0x09 */
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uint16_t intrdelay; /* 0x0C */
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uint16_t cs_status; /* 0x0E */
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uint32_t dmacapability; /* 0x10 */
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uint8_t reserved5[0x6C]; /* 0x14 */
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uint16_t chanctrl; /* 0x80 */
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uint8_t reserved6[0x2]; /* 0x82 */
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uint8_t chancmd; /* 0x84 */
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uint8_t reserved3[1]; /* 0x85 */
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uint16_t dmacount; /* 0x86 */
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uint64_t chansts; /* 0x88 */
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uint64_t chainaddr; /* 0x90 */
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uint64_t chancmp; /* 0x98 */
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uint8_t reserved2[0x8]; /* 0xA0 */
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uint32_t chanerr; /* 0xA8 */
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uint32_t chanerrmask; /* 0xAC */
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} __rte_packed;
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#define IOAT_CHANCMD_RESET 0x20
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#define IOAT_CHANCMD_SUSPEND 0x04
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#define IOAT_CHANCMP_ALIGN 8 /* CHANCMP address must be 64-bit aligned */
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#ifdef __cplusplus
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}
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#endif
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@ -7,6 +7,33 @@
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#include "ioat_hw_defs.h"
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struct ioat_dmadev {
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struct rte_dma_dev *dmadev;
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struct rte_dma_vchan_conf qcfg;
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struct rte_dma_stats stats;
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volatile uint16_t *doorbell __rte_cache_aligned;
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phys_addr_t status_addr;
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phys_addr_t ring_addr;
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struct ioat_dma_hw_desc *desc_ring;
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unsigned short next_read;
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unsigned short next_write;
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unsigned short last_write; /* Used to compute submitted count. */
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unsigned short offset; /* Used after a device recovery when counts -> 0. */
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unsigned int failure; /* Used to store chanerr for error handling. */
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/* To report completions, the device will write status back here. */
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volatile uint64_t status __rte_cache_aligned;
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/* Pointer to the register bar. */
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volatile struct ioat_registers *regs;
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/* Store the IOAT version. */
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uint8_t version;
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};
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extern int ioat_pmd_logtype;
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#define IOAT_PMD_LOG(level, fmt, args...) rte_log(RTE_LOG_ ## level, \
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