net/octeontx2: allow vector processing packets not by 4
Current vector mode implementation floor-aligns pkt count with NIX_DESCS_PER_LOOP and process that many packets. Patch addresses the case where pkt count modulo NIX_DESCS_PER_LOOP is non-zero, after the vector mode processing, scalar routine is used to process if there are any leftover packets. Scalar routine is also used when descriptor head is about to wrap and turn out to be unaligned. Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Acked-by: Jerin Jacob <jerinj@marvell.com>
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@ -130,16 +130,22 @@ nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
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const uintptr_t desc = rxq->desc;
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uint8x16_t f0, f1, f2, f3;
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uint32_t head = rxq->head;
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uint16_t pkts_left;
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pkts = nix_rx_nb_pkts(rxq, wdata, pkts, qmask);
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pkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);
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/* Packets has to be floor-aligned to NIX_DESCS_PER_LOOP */
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pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);
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while (packets < pkts) {
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/* Get the CQ pointers, since the ring size is multiple of
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* 4, We can avoid checking the wrap around of head
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* value after the each access unlike scalar version.
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*/
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/* Exit loop if head is about to wrap and become unaligned */
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if (((head + NIX_DESCS_PER_LOOP - 1) & qmask) <
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NIX_DESCS_PER_LOOP) {
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pkts_left += (pkts - packets);
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break;
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}
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const uintptr_t cq0 = desc + CQE_SZ(head);
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/* Prefetch N desc ahead */
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@ -301,6 +307,10 @@ nix_recv_pkts_vector(void *rx_queue, struct rte_mbuf **rx_pkts,
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/* Free all the CQs that we've processed */
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otx2_write64((rxq->wdata | packets), rxq->cq_door);
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if (unlikely(pkts_left))
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packets += nix_recv_pkts(rx_queue, &rx_pkts[packets],
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pkts_left, flags);
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return packets;
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}
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@ -97,7 +97,7 @@ nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,
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#define NIX_DESCS_PER_LOOP 4
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static __rte_always_inline uint16_t
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nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t pkts, const uint16_t flags)
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uint16_t pkts, uint64_t *cmd, const uint16_t flags)
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{
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uint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;
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uint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;
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@ -118,11 +118,13 @@ nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint64x2_t cmd20, cmd21;
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uint64x2_t cmd30, cmd31;
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uint64_t lmt_status, i;
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pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);
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uint16_t pkts_left;
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NIX_XMIT_FC_OR_RETURN(txq, pkts);
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pkts_left = pkts & (NIX_DESCS_PER_LOOP - 1);
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pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);
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/* Reduce the cached count */
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txq->fc_cache_pkts -= pkts;
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@ -929,17 +931,21 @@ nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
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} while (lmt_status == 0);
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}
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if (unlikely(pkts_left))
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pkts += nix_xmit_pkts(tx_queue, tx_pkts, pkts_left, cmd, flags);
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return pkts;
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}
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#else
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static __rte_always_inline uint16_t
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nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t pkts, const uint16_t flags)
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uint16_t pkts, uint64_t *cmd, const uint16_t flags)
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{
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RTE_SET_USED(tx_queue);
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RTE_SET_USED(tx_pkts);
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RTE_SET_USED(pkts);
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RTE_SET_USED(cmd);
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RTE_SET_USED(flags);
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return 0;
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}
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@ -985,12 +991,14 @@ static uint16_t __rte_noinline __hot \
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otx2_nix_xmit_pkts_vec_ ## name(void *tx_queue, \
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struct rte_mbuf **tx_pkts, uint16_t pkts) \
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{ \
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uint64_t cmd[sz]; \
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\
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/* VLAN, TSTMP, TSO is not supported by vec */ \
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if ((flags) & NIX_TX_OFFLOAD_VLAN_QINQ_F || \
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(flags) & NIX_TX_OFFLOAD_TSTAMP_F || \
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(flags) & NIX_TX_OFFLOAD_TSO_F) \
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return 0; \
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return nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, (flags)); \
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return nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd, (flags)); \
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}
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NIX_TX_FASTPATH_MODES
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