i40e/base: add parsing for CEE DCBX TLVs
This patch adds parsing for CEE DCBX TLVs from the LLDP MIB. While the driver gets the DCB CEE operational configuration from Firmware using the "Get CEE DCBX Oper Config" AQ command there is a need to get the CEE DesiredCfg Tx by firmware and DCB configuration Rx from peer; for debug and other application purposes. Also gets rid of unused locals variables. Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Tested-by: Huilong Xu <huilongx.xu@intel.com>
This commit is contained in:
Jingjing Wu
Thomas Monjalon
parent
bd6651c2d2
commit
166dceeeea
@ -298,6 +298,188 @@ static void i40e_parse_ieee_tlv(struct i40e_lldp_org_tlv *tlv,
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}
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}
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/**
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* i40e_parse_cee_pgcfg_tlv
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* @tlv: CEE DCBX PG CFG TLV
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* @dcbcfg: Local store to update ETS CFG data
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*
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* Parses CEE DCBX PG CFG TLV
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**/
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static void i40e_parse_cee_pgcfg_tlv(struct i40e_cee_feat_tlv *tlv,
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struct i40e_dcbx_config *dcbcfg)
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{
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struct i40e_dcb_ets_config *etscfg;
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u8 *buf = tlv->tlvinfo;
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u16 offset = 0;
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u8 priority;
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int i;
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etscfg = &dcbcfg->etscfg;
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if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
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etscfg->willing = 1;
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etscfg->cbs = 0;
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/* Priority Group Table (4 octets)
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* Octets:| 1 | 2 | 3 | 4 |
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* -----------------------------------------
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* |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7|
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* -----------------------------------------
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* Bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0|
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* -----------------------------------------
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*/
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for (i = 0; i < 4; i++) {
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priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_1_MASK) >>
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I40E_CEE_PGID_PRIO_1_SHIFT);
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etscfg->prioritytable[i * 2] = priority;
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priority = (u8)((buf[offset] & I40E_CEE_PGID_PRIO_0_MASK) >>
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I40E_CEE_PGID_PRIO_0_SHIFT);
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etscfg->prioritytable[i * 2 + 1] = priority;
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offset++;
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}
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/* PG Percentage Table (8 octets)
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* Octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
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* ---------------------------------
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* |pg0|pg1|pg2|pg3|pg4|pg5|pg6|pg7|
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* ---------------------------------
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*/
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for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
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etscfg->tcbwtable[i] = buf[offset++];
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/* Number of TCs supported (1 octet) */
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etscfg->maxtcs = buf[offset];
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}
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/**
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* i40e_parse_cee_pfccfg_tlv
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* @tlv: CEE DCBX PFC CFG TLV
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* @dcbcfg: Local store to update PFC CFG data
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*
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* Parses CEE DCBX PFC CFG TLV
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**/
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static void i40e_parse_cee_pfccfg_tlv(struct i40e_cee_feat_tlv *tlv,
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struct i40e_dcbx_config *dcbcfg)
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{
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u8 *buf = tlv->tlvinfo;
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if (tlv->en_will_err & I40E_CEE_FEAT_TLV_WILLING_MASK)
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dcbcfg->pfc.willing = 1;
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/* ------------------------
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* | PFC Enable | PFC TCs |
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* ------------------------
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* | 1 octet | 1 octet |
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*/
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dcbcfg->pfc.pfcenable = buf[0];
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dcbcfg->pfc.pfccap = buf[1];
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}
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/**
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* i40e_parse_cee_app_tlv
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* @tlv: CEE DCBX APP TLV
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* @dcbcfg: Local store to update APP PRIO data
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*
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* Parses CEE DCBX APP PRIO TLV
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**/
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static void i40e_parse_cee_app_tlv(struct i40e_cee_feat_tlv *tlv,
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struct i40e_dcbx_config *dcbcfg)
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{
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u16 length, typelength, offset = 0;
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struct i40e_cee_app_prio *app;
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u8 i, up, selector;
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typelength = I40E_NTOHS(tlv->hdr.typelen);
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length = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
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I40E_LLDP_TLV_LEN_SHIFT);
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dcbcfg->numapps = length/sizeof(*app);
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if (!dcbcfg->numapps)
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return;
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for (i = 0; i < dcbcfg->numapps; i++) {
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app = (struct i40e_cee_app_prio *)(tlv->tlvinfo + offset);
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for (up = 0; up < I40E_MAX_USER_PRIORITY; up++) {
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if (app->prio_map & BIT(up))
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break;
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}
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dcbcfg->app[i].priority = up;
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/* Get Selector from lower 2 bits, and convert to IEEE */
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selector = (app->upper_oui_sel & I40E_CEE_APP_SELECTOR_MASK);
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if (selector == I40E_CEE_APP_SEL_ETHTYPE)
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dcbcfg->app[i].selector = I40E_APP_SEL_ETHTYPE;
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else if (selector == I40E_CEE_APP_SEL_TCPIP)
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dcbcfg->app[i].selector = I40E_APP_SEL_TCPIP;
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else
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/* Keep selector as it is for unknown types */
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dcbcfg->app[i].selector = selector;
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dcbcfg->app[i].protocolid = I40E_NTOHS(app->protocol);
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/* Move to next app */
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offset += sizeof(*app);
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}
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}
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/**
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* i40e_parse_cee_tlv
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* @tlv: CEE DCBX TLV
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* @dcbcfg: Local store to update DCBX config data
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*
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* Get the TLV subtype and send it to parsing function
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* based on the subtype value
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**/
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static void i40e_parse_cee_tlv(struct i40e_lldp_org_tlv *tlv,
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struct i40e_dcbx_config *dcbcfg)
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{
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u16 len, tlvlen, sublen, typelength;
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struct i40e_cee_feat_tlv *sub_tlv;
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u8 subtype, feat_tlv_count = 0;
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u32 ouisubtype;
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ouisubtype = I40E_NTOHL(tlv->ouisubtype);
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subtype = (u8)((ouisubtype & I40E_LLDP_TLV_SUBTYPE_MASK) >>
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I40E_LLDP_TLV_SUBTYPE_SHIFT);
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/* Return if not CEE DCBX */
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if (subtype != I40E_CEE_DCBX_TYPE)
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return;
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typelength = I40E_NTOHS(tlv->typelength);
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tlvlen = (u16)((typelength & I40E_LLDP_TLV_LEN_MASK) >>
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I40E_LLDP_TLV_LEN_SHIFT);
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len = sizeof(tlv->typelength) + sizeof(ouisubtype) +
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sizeof(struct i40e_cee_ctrl_tlv);
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/* Return if no CEE DCBX Feature TLVs */
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if (tlvlen <= len)
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return;
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sub_tlv = (struct i40e_cee_feat_tlv *)((char *)tlv + len);
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while (feat_tlv_count < I40E_CEE_MAX_FEAT_TYPE) {
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typelength = I40E_NTOHS(sub_tlv->hdr.typelen);
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sublen = (u16)((typelength &
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I40E_LLDP_TLV_LEN_MASK) >>
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I40E_LLDP_TLV_LEN_SHIFT);
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subtype = (u8)((typelength & I40E_LLDP_TLV_TYPE_MASK) >>
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I40E_LLDP_TLV_TYPE_SHIFT);
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switch (subtype) {
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case I40E_CEE_SUBTYPE_PG_CFG:
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i40e_parse_cee_pgcfg_tlv(sub_tlv, dcbcfg);
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break;
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case I40E_CEE_SUBTYPE_PFC_CFG:
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i40e_parse_cee_pfccfg_tlv(sub_tlv, dcbcfg);
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break;
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case I40E_CEE_SUBTYPE_APP_PRI:
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i40e_parse_cee_app_tlv(sub_tlv, dcbcfg);
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break;
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default:
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return; /* Invalid Sub-type return */
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}
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feat_tlv_count++;
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/* Move to next sub TLV */
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sub_tlv = (struct i40e_cee_feat_tlv *)((char *)sub_tlv +
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sizeof(sub_tlv->hdr.typelen) +
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sublen);
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}
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}
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/**
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* i40e_parse_org_tlv
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* @tlv: Organization specific TLV
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@ -319,6 +501,9 @@ static void i40e_parse_org_tlv(struct i40e_lldp_org_tlv *tlv,
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case I40E_IEEE_8021QAZ_OUI:
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i40e_parse_ieee_tlv(tlv, dcbcfg);
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break;
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case I40E_CEE_DCBX_OUI:
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i40e_parse_cee_tlv(tlv, dcbcfg);
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break;
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default:
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break;
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}
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@ -426,7 +611,7 @@ static void i40e_cee_to_dcb_v1_config(
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{
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u16 status, tlv_status = LE16_TO_CPU(cee_cfg->tlv_status);
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u16 app_prio = LE16_TO_CPU(cee_cfg->oper_app_prio);
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u8 i, tc, err, sync, oper;
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u8 i, tc, err;
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/* CEE PG data to ETS config */
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dcbcfg->etscfg.maxtcs = cee_cfg->oper_num_tc;
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@ -466,9 +651,7 @@ static void i40e_cee_to_dcb_v1_config(
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status = (tlv_status & I40E_AQC_CEE_APP_STATUS_MASK) >>
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I40E_AQC_CEE_APP_STATUS_SHIFT;
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err = (status & I40E_TLV_STATUS_ERR) ? 1 : 0;
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sync = (status & I40E_TLV_STATUS_SYNC) ? 1 : 0;
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oper = (status & I40E_TLV_STATUS_OPER) ? 1 : 0;
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/* Add APPs if Error is False and Oper/Sync is True */
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/* Add APPs if Error is False */
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if (!err) {
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/* CEE operating configuration supports FCoE/iSCSI/FIP only */
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dcbcfg->numapps = I40E_CEE_OPER_MAX_APPS;
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@ -54,6 +54,15 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_IEEE_SUBTYPE_PFC_CFG 11
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#define I40E_IEEE_SUBTYPE_APP_PRI 12
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#define I40E_CEE_DCBX_OUI 0x001b21
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#define I40E_CEE_DCBX_TYPE 2
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#define I40E_CEE_SUBTYPE_CTRL 1
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#define I40E_CEE_SUBTYPE_PG_CFG 2
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#define I40E_CEE_SUBTYPE_PFC_CFG 3
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#define I40E_CEE_SUBTYPE_APP_PRI 4
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#define I40E_CEE_MAX_FEAT_TYPE 3
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#define I40E_LLDP_ADMINSTATUS_DISABLED 0
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#define I40E_LLDP_ADMINSTATUS_ENABLED_RX 1
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#define I40E_LLDP_ADMINSTATUS_ENABLED_TX 2
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@ -136,6 +145,36 @@ struct i40e_lldp_org_tlv {
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__be32 ouisubtype;
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u8 tlvinfo[1];
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};
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struct i40e_cee_tlv_hdr {
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__be16 typelen;
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u8 operver;
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u8 maxver;
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};
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struct i40e_cee_ctrl_tlv {
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struct i40e_cee_tlv_hdr hdr;
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__be32 seqno;
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__be32 ackno;
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};
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struct i40e_cee_feat_tlv {
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struct i40e_cee_tlv_hdr hdr;
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u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
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#define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80
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#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40
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#define I40E_CEE_FEAT_TLV_ERR_MASK 0x20
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u8 subtype;
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u8 tlvinfo[1];
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};
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struct i40e_cee_app_prio {
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__be16 protocol;
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u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
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#define I40E_CEE_APP_SELECTOR_MASK 0x03
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__be16 lower_oui;
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u8 prio_map;
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};
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#pragma pack()
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/*
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@ -490,6 +490,8 @@ struct i40e_fc_info {
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#define I40E_APP_PROTOID_FIP 0x8914
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#define I40E_APP_SEL_ETHTYPE 0x1
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#define I40E_APP_SEL_TCPIP 0x2
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#define I40E_CEE_APP_SEL_ETHTYPE 0x0
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#define I40E_CEE_APP_SEL_TCPIP 0x1
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/* CEE or IEEE 802.1Qaz ETS Configuration data */
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struct i40e_dcb_ets_config {
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