crypto/octeontx2: add enqueue/dequeue ops
This patch adds the enqueue burst and dequeue burst callbacks for the OCTEON TX2 crypto driver. Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com> Signed-off-by: Anoob Joseph <anoobj@marvell.com> Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This commit is contained in:
Anoob Joseph
Akhil Goyal
parent
3e72548830
commit
17ac2a7219
@ -197,6 +197,44 @@ typedef union cpt_inst_s {
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};
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#endif /* Word 7 - End */
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} s8x;
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struct cpt_inst_s_9s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t nixtx_addr : 60;
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uint64_t doneint : 1;
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uint64_t nixtxl : 3;
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#else /* Word 0 - Little Endian */
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uint64_t nixtxl : 3;
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uint64_t doneint : 1;
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uint64_t nixtx_addr : 60;
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#endif /* Word 0 - End */
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uint64_t res_addr;
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */
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uint64_t rvu_pf_func : 16;
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uint64_t reserved_172_175 : 4;
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uint64_t grp : 10;
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uint64_t tt : 2;
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uint64_t tag : 32;
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#else /* Word 2 - Little Endian */
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uint64_t tag : 32;
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uint64_t tt : 2;
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uint64_t grp : 10;
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uint64_t reserved_172_175 : 4;
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uint64_t rvu_pf_func : 16;
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#endif /* Word 2 - End */
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */
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uint64_t wq_ptr : 61;
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uint64_t reserved_194_193 : 2;
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uint64_t qord : 1;
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#else /* Word 3 - Little Endian */
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uint64_t qord : 1;
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uint64_t reserved_194_193 : 2;
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uint64_t wq_ptr : 61;
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#endif /* Word 3 - End */
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uint64_t ei0;
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uint64_t ei1;
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uint64_t ei2;
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uint64_t ei3;
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} s9x;
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} cpt_inst_s_t;
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/**
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@ -243,6 +281,20 @@ typedef union cpt_res_s {
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uint64_t reserved_64_127 : 64;
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#endif /* Word 1 - End */
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} s8x;
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struct cpt_res_s_9s {
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#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */
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uint64_t reserved_17_63:47;
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uint64_t doneint:1;
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uint64_t uc_compcode:8;
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uint64_t compcode:8;
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#else /* Word 0 - Little Endian */
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uint64_t compcode:8;
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uint64_t uc_compcode:8;
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uint64_t doneint:1;
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uint64_t reserved_17_63:47;
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#endif /* Word 0 - End */
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uint64_t reserved_64_127;
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} s9x;
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} cpt_res_s_t;
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/**
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@ -24,6 +24,7 @@ CFLAGS += -O3
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CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
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CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
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CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2
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CFLAGS += -DALLOW_EXPERIMENTAL_API
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ifneq ($(CONFIG_RTE_ARCH_64),y)
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CFLAGS += -Wno-int-to-pointer-cast
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@ -10,6 +10,7 @@ deps += ['common_cpt']
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deps += ['common_octeontx2']
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name = 'octeontx2_crypto'
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allow_experimental_apis = true
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sources = files('otx2_cryptodev.c',
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'otx2_cryptodev_capabilities.c',
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'otx2_cryptodev_hw_access.c',
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@ -12,6 +12,7 @@
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#include "cpt_common.h"
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#include "cpt_hw_types.h"
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#include "cpt_mcode_defines.h"
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#include "otx2_dev.h"
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@ -119,6 +120,21 @@ union otx2_cpt_lf_q_grp_ptr {
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} s;
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};
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/*
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* Enumeration cpt_9x_comp_e
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*
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* CPT 9X Completion Enumeration
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* Enumerates the values of CPT_RES_S[COMPCODE].
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*/
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enum cpt_9x_comp_e {
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CPT_9X_COMP_E_NOTDONE = 0x00,
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CPT_9X_COMP_E_GOOD = 0x01,
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CPT_9X_COMP_E_FAULT = 0x02,
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CPT_9X_COMP_E_HWERR = 0x04,
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CPT_9X_COMP_E_INSTERR = 0x05,
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CPT_9X_COMP_E_LAST_ENTRY = 0x06
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};
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struct otx2_cpt_qp {
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uint32_t id;
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/**< Queue pair id */
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@ -329,6 +329,292 @@ sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)
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rte_mempool_put(pool, priv);
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}
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static __rte_always_inline int32_t __hot
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otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
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struct pending_queue *pend_q,
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struct cpt_request_info *req)
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{
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void *lmtline = qp->lmtline;
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union cpt_inst_s inst;
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uint64_t lmt_status;
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if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
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return -EAGAIN;
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inst.u[0] = 0;
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inst.s9x.res_addr = req->comp_baddr;
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inst.u[2] = 0;
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inst.u[3] = 0;
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inst.s9x.ei0 = req->ist.ei0;
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inst.s9x.ei1 = req->ist.ei1;
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inst.s9x.ei2 = req->ist.ei2;
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inst.s9x.ei3 = req->ist.ei3;
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req->time_out = rte_get_timer_cycles() +
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DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
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do {
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/* Copy CPT command to LMTLINE */
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memcpy(lmtline, &inst, sizeof(inst));
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/*
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* Make sure compiler does not reorder memcpy and ldeor.
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* LMTST transactions are always flushed from the write
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* buffer immediately, a DMB is not required to push out
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* LMTSTs.
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*/
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rte_cio_wmb();
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lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
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} while (lmt_status == 0);
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pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
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/* We will use soft queue length here to limit requests */
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MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
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pend_q->pending_count += 1;
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return 0;
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}
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static __rte_always_inline int __hot
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otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
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struct pending_queue *pend_q)
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{
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struct rte_crypto_sym_op *sym_op = op->sym;
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struct cpt_request_info *req;
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struct cpt_sess_misc *sess;
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vq_cmd_word3_t *w3;
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uint64_t cpt_op;
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void *mdata;
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int ret;
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sess = get_sym_session_private_data(sym_op->session,
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otx2_cryptodev_driver_id);
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cpt_op = sess->cpt_op;
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if (cpt_op & CPT_OP_CIPHER_MASK)
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ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
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(void **)&req);
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else
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ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
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(void **)&req);
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if (unlikely(ret)) {
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CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
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op, (unsigned int)cpt_op, ret);
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return ret;
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}
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w3 = ((vq_cmd_word3_t *)(&req->ist.ei3));
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w3->s.grp = sess->egrp;
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ret = otx2_cpt_enqueue_req(qp, pend_q, req);
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if (unlikely(ret)) {
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/* Free buffer allocated by fill params routines */
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free_op_meta(mdata, qp->meta_info.pool);
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}
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return ret;
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}
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static __rte_always_inline int __hot
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otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
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struct pending_queue *pend_q)
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{
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const int driver_id = otx2_cryptodev_driver_id;
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struct rte_crypto_sym_op *sym_op = op->sym;
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struct rte_cryptodev_sym_session *sess;
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int ret;
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/* Create temporary session */
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if (rte_mempool_get(qp->sess_mp, (void **)&sess))
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return -ENOMEM;
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ret = sym_session_configure(driver_id, sym_op->xform, sess,
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qp->sess_mp_priv);
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if (ret)
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goto sess_put;
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sym_op->session = sess;
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ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
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if (unlikely(ret))
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goto priv_put;
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return 0;
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priv_put:
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sym_session_clear(driver_id, sess);
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sess_put:
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rte_mempool_put(qp->sess_mp, sess);
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return ret;
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}
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static uint16_t
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otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
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{
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uint16_t nb_allowed, count = 0;
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struct otx2_cpt_qp *qp = qptr;
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struct pending_queue *pend_q;
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struct rte_crypto_op *op;
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int ret;
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pend_q = &qp->pend_q;
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nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
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if (nb_ops > nb_allowed)
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nb_ops = nb_allowed;
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for (count = 0; count < nb_ops; count++) {
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op = ops[count];
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if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
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if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
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ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
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else
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ret = otx2_cpt_enqueue_sym_sessless(qp, op,
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pend_q);
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} else
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break;
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if (unlikely(ret))
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break;
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}
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return count;
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}
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static inline void
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otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
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uintptr_t *rsp, uint8_t cc)
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{
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if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
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if (likely(cc == NO_ERR)) {
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/* Verify authentication data if required */
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if (unlikely(rsp[2]))
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compl_auth_verify(cop, (uint8_t *)rsp[2],
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rsp[3]);
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else
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cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
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} else {
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if (cc == ERR_GC_ICV_MISCOMPARE)
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cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
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else
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cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
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}
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if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
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sym_session_clear(otx2_cryptodev_driver_id,
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cop->sym->session);
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rte_mempool_put(qp->sess_mp, cop->sym->session);
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cop->sym->session = NULL;
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}
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}
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}
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static __rte_always_inline uint8_t
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otx2_cpt_compcode_get(struct cpt_request_info *req)
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{
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volatile struct cpt_res_s_9s *res;
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uint8_t ret;
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res = (volatile struct cpt_res_s_9s *)req->completion_addr;
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if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) {
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if (rte_get_timer_cycles() < req->time_out)
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return ERR_REQ_PENDING;
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CPT_LOG_DP_ERR("Request timed out");
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return ERR_REQ_TIMEOUT;
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}
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if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) {
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ret = NO_ERR;
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if (unlikely(res->uc_compcode)) {
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ret = res->uc_compcode;
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CPT_LOG_DP_DEBUG("Request failed with microcode error");
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CPT_LOG_DP_DEBUG("MC completion code 0x%x",
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res->uc_compcode);
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}
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} else {
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CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode);
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ret = res->compcode;
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switch (res->compcode) {
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case CPT_9X_COMP_E_INSTERR:
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CPT_LOG_DP_ERR("Request failed with instruction error");
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break;
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case CPT_9X_COMP_E_FAULT:
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CPT_LOG_DP_ERR("Request failed with DMA fault");
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break;
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case CPT_9X_COMP_E_HWERR:
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CPT_LOG_DP_ERR("Request failed with hardware error");
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break;
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default:
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CPT_LOG_DP_ERR("Request failed with unknown completion code");
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}
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}
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return ret;
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}
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static uint16_t
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otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
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{
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int i, nb_pending, nb_completed;
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struct otx2_cpt_qp *qp = qptr;
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struct pending_queue *pend_q;
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struct cpt_request_info *req;
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struct rte_crypto_op *cop;
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uint8_t cc[nb_ops];
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struct rid *rid;
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uintptr_t *rsp;
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void *metabuf;
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pend_q = &qp->pend_q;
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nb_pending = pend_q->pending_count;
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if (nb_ops > nb_pending)
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nb_ops = nb_pending;
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for (i = 0; i < nb_ops; i++) {
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rid = &pend_q->rid_queue[pend_q->deq_head];
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req = (struct cpt_request_info *)(rid->rid);
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cc[i] = otx2_cpt_compcode_get(req);
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if (unlikely(cc[i] == ERR_REQ_PENDING))
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break;
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ops[i] = req->op;
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MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
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pend_q->pending_count -= 1;
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}
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nb_completed = i;
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for (i = 0; i < nb_completed; i++) {
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rsp = (void *)ops[i];
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metabuf = (void *)rsp[0];
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cop = (void *)rsp[1];
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ops[i] = cop;
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otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
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free_op_meta(metabuf, qp->meta_info.pool);
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}
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return nb_completed;
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}
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/* PMD ops */
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static int
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@ -378,6 +664,9 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev,
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goto queues_detach;
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}
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dev->enqueue_burst = otx2_cpt_enqueue_burst;
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dev->dequeue_burst = otx2_cpt_dequeue_burst;
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rte_mb();
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return 0;
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