net/ice: support basic Rx/Tx
Add basic RX & TX support. Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com> Signed-off-by: Qiming Yang <qiming.yang@intel.com> Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com> Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com> Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
This commit is contained in:
Wenzhuo Lu
Ferruh Yigit
parent
ab9dccf09a
commit
17c7d0f9d6
@ -8,6 +8,11 @@ Speed capabilities = Y
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Link status = Y
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Link status event = Y
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Queue start/stop = Y
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TSO = Y
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CRC offload = Y
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L3 checksum offload = Y
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L4 checksum offload = Y
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Packet type parsing = Y
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BSD nic_uio = Y
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Linux UIO = Y
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Linux VFIO = Y
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@ -681,6 +681,9 @@ ice_dev_init(struct rte_eth_dev *dev)
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int ret;
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dev->dev_ops = &ice_eth_dev_ops;
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dev->rx_pkt_burst = ice_recv_pkts;
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dev->tx_pkt_burst = ice_xmit_pkts;
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dev->tx_pkt_prepare = ice_prep_pkts;
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ice_set_default_ptype_table(dev);
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pci_dev = RTE_DEV_TO_PCI(dev->device);
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@ -962,6 +965,8 @@ ice_dev_start(struct rte_eth_dev *dev)
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goto rx_err;
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}
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ice_set_rx_function(dev);
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ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
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((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
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ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
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@ -1029,14 +1034,60 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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dev_info->max_mac_addrs = vsi->max_macaddrs;
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dev_info->max_vfs = pci_dev->max_vfs;
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dev_info->rx_offload_capa = 0;
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dev_info->tx_offload_capa = 0;
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dev_info->rx_offload_capa =
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DEV_RX_OFFLOAD_IPV4_CKSUM |
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DEV_RX_OFFLOAD_UDP_CKSUM |
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DEV_RX_OFFLOAD_TCP_CKSUM |
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DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
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DEV_RX_OFFLOAD_KEEP_CRC;
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dev_info->tx_offload_capa =
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DEV_TX_OFFLOAD_IPV4_CKSUM |
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DEV_TX_OFFLOAD_UDP_CKSUM |
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DEV_TX_OFFLOAD_TCP_CKSUM |
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DEV_TX_OFFLOAD_SCTP_CKSUM |
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
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DEV_TX_OFFLOAD_TCP_TSO |
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DEV_TX_OFFLOAD_MULTI_SEGS;
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dev_info->rx_queue_offload_capa = 0;
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dev_info->tx_queue_offload_capa = 0;
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dev_info->reta_size = hw->func_caps.common_cap.rss_table_size;
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dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
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dev_info->default_rxconf = (struct rte_eth_rxconf) {
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.rx_thresh = {
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.pthresh = ICE_DEFAULT_RX_PTHRESH,
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.hthresh = ICE_DEFAULT_RX_HTHRESH,
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.wthresh = ICE_DEFAULT_RX_WTHRESH,
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},
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.rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
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.rx_drop_en = 0,
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.offloads = 0,
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};
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dev_info->default_txconf = (struct rte_eth_txconf) {
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.tx_thresh = {
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.pthresh = ICE_DEFAULT_TX_PTHRESH,
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.hthresh = ICE_DEFAULT_TX_HTHRESH,
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.wthresh = ICE_DEFAULT_TX_WTHRESH,
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},
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.tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
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.tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
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.offloads = 0,
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};
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dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
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.nb_max = ICE_MAX_RING_DESC,
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.nb_min = ICE_MIN_RING_DESC,
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.nb_align = ICE_ALIGN_RING_DESC,
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};
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dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
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.nb_max = ICE_MAX_RING_DESC,
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.nb_min = ICE_MIN_RING_DESC,
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.nb_align = ICE_ALIGN_RING_DESC,
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};
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dev_info->speed_capa = ETH_LINK_SPEED_10M |
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ETH_LINK_SPEED_100M |
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ETH_LINK_SPEED_1G |
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@ -946,8 +946,36 @@ ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
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return desc;
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}
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/* Rx L3/L4 checksum */
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static inline uint64_t
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ice_rxd_error_to_pkt_flags(uint64_t qword)
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{
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uint64_t flags = 0;
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uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
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if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
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flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
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return flags;
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}
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if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
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flags |= PKT_RX_IP_CKSUM_BAD;
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else
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flags |= PKT_RX_IP_CKSUM_GOOD;
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if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
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flags |= PKT_RX_L4_CKSUM_BAD;
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else
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flags |= PKT_RX_L4_CKSUM_GOOD;
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if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
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flags |= PKT_RX_EIP_CKSUM_BAD;
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return flags;
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}
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const uint32_t *
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ice_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
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ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
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{
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static const uint32_t ptypes[] = {
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/* refers to ice_get_default_pkt_type() */
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@ -979,7 +1007,9 @@ ice_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
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RTE_PTYPE_UNKNOWN
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};
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return ptypes;
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if (dev->rx_pkt_burst == ice_recv_pkts)
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return ptypes;
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return NULL;
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}
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void
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@ -1024,6 +1054,467 @@ ice_free_queues(struct rte_eth_dev *dev)
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dev->data->nb_tx_queues = 0;
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}
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uint16_t
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ice_recv_pkts(void *rx_queue,
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struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts)
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{
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struct ice_rx_queue *rxq = rx_queue;
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volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
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volatile union ice_rx_desc *rxdp;
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struct ice_rx_entry *sw_ring = rxq->sw_ring;
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struct ice_rx_entry *rxe;
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struct rte_mbuf *nmb; /* new allocated mbuf */
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struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
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uint16_t rx_id = rxq->rx_tail;
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uint16_t nb_rx = 0;
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uint16_t nb_hold = 0;
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uint16_t rx_packet_len;
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uint32_t rx_status;
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uint64_t qword1;
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uint64_t dma_addr;
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uint64_t pkt_flags = 0;
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uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
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struct rte_eth_dev *dev;
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while (nb_rx < nb_pkts) {
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rxdp = &rx_ring[rx_id];
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qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
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rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
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ICE_RXD_QW1_STATUS_S;
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/* Check the DD bit first */
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if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
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break;
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/* allocate mbuf */
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nmb = rte_mbuf_raw_alloc(rxq->mp);
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if (unlikely(!nmb)) {
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dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
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dev->data->rx_mbuf_alloc_failed++;
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break;
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}
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nb_hold++;
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rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
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rx_id++;
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if (unlikely(rx_id == rxq->nb_rx_desc))
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rx_id = 0;
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rxm = rxe->mbuf;
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rxe->mbuf = nmb;
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dma_addr =
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rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
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/**
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* fill the read format of descriptor with physic address in
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* new allocated mbuf: nmb
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*/
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rxdp->read.hdr_addr = 0;
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rxdp->read.pkt_addr = dma_addr;
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/* calculate rx_packet_len of the received pkt */
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rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
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ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
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/* fill old mbuf with received descriptor: rxd */
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rxm->data_off = RTE_PKTMBUF_HEADROOM;
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rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
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rxm->nb_segs = 1;
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rxm->next = NULL;
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rxm->pkt_len = rx_packet_len;
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rxm->data_len = rx_packet_len;
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rxm->port = rxq->port_id;
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rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
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ICE_RXD_QW1_PTYPE_M) >>
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ICE_RXD_QW1_PTYPE_S)];
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pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
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rxm->ol_flags |= pkt_flags;
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/* copy old mbuf to rx_pkts */
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rx_pkts[nb_rx++] = rxm;
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}
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rxq->rx_tail = rx_id;
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/**
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* If the number of free RX descriptors is greater than the RX free
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* threshold of the queue, advance the receive tail register of queue.
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* Update that register with the value of the last processed RX
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* descriptor minus 1.
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*/
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nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
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if (nb_hold > rxq->rx_free_thresh) {
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rx_id = (uint16_t)(rx_id == 0 ?
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(rxq->nb_rx_desc - 1) : (rx_id - 1));
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/* write TAIL register */
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ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
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nb_hold = 0;
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}
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rxq->nb_rx_hold = nb_hold;
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/* return received packet in the burst */
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return nb_rx;
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}
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static inline void
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ice_txd_enable_checksum(uint64_t ol_flags,
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uint32_t *td_cmd,
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uint32_t *td_offset,
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union ice_tx_offload tx_offload)
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{
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/* L2 length must be set. */
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*td_offset |= (tx_offload.l2_len >> 1) <<
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ICE_TX_DESC_LEN_MACLEN_S;
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/* Enable L3 checksum offloads */
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if (ol_flags & PKT_TX_IP_CKSUM) {
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*td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
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*td_offset |= (tx_offload.l3_len >> 2) <<
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ICE_TX_DESC_LEN_IPLEN_S;
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} else if (ol_flags & PKT_TX_IPV4) {
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*td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
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*td_offset |= (tx_offload.l3_len >> 2) <<
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ICE_TX_DESC_LEN_IPLEN_S;
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} else if (ol_flags & PKT_TX_IPV6) {
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*td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
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*td_offset |= (tx_offload.l3_len >> 2) <<
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ICE_TX_DESC_LEN_IPLEN_S;
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}
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if (ol_flags & PKT_TX_TCP_SEG) {
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*td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
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*td_offset |= (tx_offload.l4_len >> 2) <<
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ICE_TX_DESC_LEN_L4_LEN_S;
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return;
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}
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/* Enable L4 checksum offloads */
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switch (ol_flags & PKT_TX_L4_MASK) {
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case PKT_TX_TCP_CKSUM:
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*td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
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*td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
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ICE_TX_DESC_LEN_L4_LEN_S;
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break;
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case PKT_TX_SCTP_CKSUM:
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*td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
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*td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
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ICE_TX_DESC_LEN_L4_LEN_S;
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break;
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case PKT_TX_UDP_CKSUM:
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*td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
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*td_offset |= (sizeof(struct udp_hdr) >> 2) <<
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ICE_TX_DESC_LEN_L4_LEN_S;
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break;
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default:
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break;
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}
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}
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static inline int
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ice_xmit_cleanup(struct ice_tx_queue *txq)
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{
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struct ice_tx_entry *sw_ring = txq->sw_ring;
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volatile struct ice_tx_desc *txd = txq->tx_ring;
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uint16_t last_desc_cleaned = txq->last_desc_cleaned;
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uint16_t nb_tx_desc = txq->nb_tx_desc;
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uint16_t desc_to_clean_to;
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uint16_t nb_tx_to_clean;
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/* Determine the last descriptor needing to be cleaned */
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desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
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if (desc_to_clean_to >= nb_tx_desc)
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desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
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/* Check to make sure the last descriptor to clean is done */
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desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
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if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
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rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
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PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
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"(port=%d queue=%d) value=0x%"PRIx64"\n",
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desc_to_clean_to,
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txq->port_id, txq->queue_id,
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txd[desc_to_clean_to].cmd_type_offset_bsz);
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/* Failed to clean any descriptors */
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return -1;
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}
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/* Figure out how many descriptors will be cleaned */
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if (last_desc_cleaned > desc_to_clean_to)
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nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
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desc_to_clean_to);
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else
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nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
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last_desc_cleaned);
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/* The last descriptor to clean is done, so that means all the
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* descriptors from the last descriptor that was cleaned
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* up to the last descriptor with the RS bit set
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* are done. Only reset the threshold descriptor.
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*/
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txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
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/* Update the txq to reflect the last descriptor that was cleaned */
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txq->last_desc_cleaned = desc_to_clean_to;
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txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
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return 0;
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}
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/* Check if the context descriptor is needed for TX offloading */
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static inline uint16_t
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ice_calc_context_desc(uint64_t flags)
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{
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static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;
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return (flags & mask) ? 1 : 0;
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}
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/* set ice TSO context descriptor */
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static inline uint64_t
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ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
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{
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uint64_t ctx_desc = 0;
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uint32_t cd_cmd, hdr_len, cd_tso_len;
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if (!tx_offload.l4_len) {
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PMD_TX_LOG(DEBUG, "L4 length set to 0");
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return ctx_desc;
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}
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/**
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* in case of non tunneling packet, the outer_l2_len and
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* outer_l3_len must be 0.
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*/
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hdr_len = tx_offload.outer_l2_len +
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tx_offload.outer_l3_len +
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tx_offload.l2_len +
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tx_offload.l3_len +
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tx_offload.l4_len;
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cd_cmd = ICE_TX_CTX_DESC_TSO;
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cd_tso_len = mbuf->pkt_len - hdr_len;
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ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
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((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
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((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
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return ctx_desc;
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}
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uint16_t
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ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
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{
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struct ice_tx_queue *txq;
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volatile struct ice_tx_desc *tx_ring;
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volatile struct ice_tx_desc *txd;
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struct ice_tx_entry *sw_ring;
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struct ice_tx_entry *txe, *txn;
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struct rte_mbuf *tx_pkt;
|
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struct rte_mbuf *m_seg;
|
||||
uint16_t tx_id;
|
||||
uint16_t nb_tx;
|
||||
uint16_t nb_used;
|
||||
uint16_t nb_ctx;
|
||||
uint32_t td_cmd = 0;
|
||||
uint32_t td_offset = 0;
|
||||
uint32_t td_tag = 0;
|
||||
uint16_t tx_last;
|
||||
uint64_t buf_dma_addr;
|
||||
uint64_t ol_flags;
|
||||
union ice_tx_offload tx_offload = {0};
|
||||
|
||||
txq = tx_queue;
|
||||
sw_ring = txq->sw_ring;
|
||||
tx_ring = txq->tx_ring;
|
||||
tx_id = txq->tx_tail;
|
||||
txe = &sw_ring[tx_id];
|
||||
|
||||
/* Check if the descriptor ring needs to be cleaned. */
|
||||
if (txq->nb_tx_free < txq->tx_free_thresh)
|
||||
ice_xmit_cleanup(txq);
|
||||
|
||||
for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
|
||||
tx_pkt = *tx_pkts++;
|
||||
|
||||
td_cmd = 0;
|
||||
ol_flags = tx_pkt->ol_flags;
|
||||
tx_offload.l2_len = tx_pkt->l2_len;
|
||||
tx_offload.l3_len = tx_pkt->l3_len;
|
||||
tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
|
||||
tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
|
||||
tx_offload.l4_len = tx_pkt->l4_len;
|
||||
tx_offload.tso_segsz = tx_pkt->tso_segsz;
|
||||
/* Calculate the number of context descriptors needed. */
|
||||
nb_ctx = ice_calc_context_desc(ol_flags);
|
||||
|
||||
/* The number of descriptors that must be allocated for
|
||||
* a packet equals to the number of the segments of that
|
||||
* packet plus the number of context descriptor if needed.
|
||||
*/
|
||||
nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
|
||||
tx_last = (uint16_t)(tx_id + nb_used - 1);
|
||||
|
||||
/* Circular ring */
|
||||
if (tx_last >= txq->nb_tx_desc)
|
||||
tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
|
||||
|
||||
if (nb_used > txq->nb_tx_free) {
|
||||
if (ice_xmit_cleanup(txq) != 0) {
|
||||
if (nb_tx == 0)
|
||||
return 0;
|
||||
goto end_of_tx;
|
||||
}
|
||||
if (unlikely(nb_used > txq->tx_rs_thresh)) {
|
||||
while (nb_used > txq->nb_tx_free) {
|
||||
if (ice_xmit_cleanup(txq) != 0) {
|
||||
if (nb_tx == 0)
|
||||
return 0;
|
||||
goto end_of_tx;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable checksum offloading */
|
||||
if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
|
||||
ice_txd_enable_checksum(ol_flags, &td_cmd,
|
||||
&td_offset, tx_offload);
|
||||
}
|
||||
|
||||
if (nb_ctx) {
|
||||
/* Setup TX context descriptor if required */
|
||||
uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
|
||||
|
||||
txn = &sw_ring[txe->next_id];
|
||||
RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
|
||||
if (txe->mbuf) {
|
||||
rte_pktmbuf_free_seg(txe->mbuf);
|
||||
txe->mbuf = NULL;
|
||||
}
|
||||
|
||||
if (ol_flags & PKT_TX_TCP_SEG)
|
||||
cd_type_cmd_tso_mss |=
|
||||
ice_set_tso_ctx(tx_pkt, tx_offload);
|
||||
|
||||
txe->last_id = tx_last;
|
||||
tx_id = txe->next_id;
|
||||
txe = txn;
|
||||
}
|
||||
m_seg = tx_pkt;
|
||||
|
||||
do {
|
||||
txd = &tx_ring[tx_id];
|
||||
txn = &sw_ring[txe->next_id];
|
||||
|
||||
if (txe->mbuf)
|
||||
rte_pktmbuf_free_seg(txe->mbuf);
|
||||
txe->mbuf = m_seg;
|
||||
|
||||
/* Setup TX Descriptor */
|
||||
buf_dma_addr = rte_mbuf_data_iova(m_seg);
|
||||
txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
|
||||
txd->cmd_type_offset_bsz =
|
||||
rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
|
||||
((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
|
||||
((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
|
||||
((uint64_t)m_seg->data_len <<
|
||||
ICE_TXD_QW1_TX_BUF_SZ_S) |
|
||||
((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
|
||||
|
||||
txe->last_id = tx_last;
|
||||
tx_id = txe->next_id;
|
||||
txe = txn;
|
||||
m_seg = m_seg->next;
|
||||
} while (m_seg);
|
||||
|
||||
/* fill the last descriptor with End of Packet (EOP) bit */
|
||||
td_cmd |= ICE_TX_DESC_CMD_EOP;
|
||||
txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
|
||||
txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
|
||||
|
||||
/* set RS bit on the last descriptor of one packet */
|
||||
if (txq->nb_tx_used >= txq->tx_rs_thresh) {
|
||||
PMD_TX_FREE_LOG(DEBUG,
|
||||
"Setting RS bit on TXD id="
|
||||
"%4u (port=%d queue=%d)",
|
||||
tx_last, txq->port_id, txq->queue_id);
|
||||
|
||||
td_cmd |= ICE_TX_DESC_CMD_RS;
|
||||
|
||||
/* Update txq RS bit counters */
|
||||
txq->nb_tx_used = 0;
|
||||
}
|
||||
txd->cmd_type_offset_bsz |=
|
||||
rte_cpu_to_le_64(((uint64_t)td_cmd) <<
|
||||
ICE_TXD_QW1_CMD_S);
|
||||
}
|
||||
end_of_tx:
|
||||
rte_wmb();
|
||||
|
||||
/* update Tail register */
|
||||
ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
|
||||
txq->tx_tail = tx_id;
|
||||
|
||||
return nb_tx;
|
||||
}
|
||||
|
||||
void __attribute__((cold))
|
||||
ice_set_rx_function(struct rte_eth_dev *dev)
|
||||
{
|
||||
dev->rx_pkt_burst = ice_recv_pkts;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* TX prep functions
|
||||
*
|
||||
**********************************************************************/
|
||||
/* The default values of TSO MSS */
|
||||
#define ICE_MIN_TSO_MSS 64
|
||||
#define ICE_MAX_TSO_MSS 9728
|
||||
#define ICE_MAX_TSO_FRAME_SIZE 262144
|
||||
uint16_t
|
||||
ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t nb_pkts)
|
||||
{
|
||||
int i, ret;
|
||||
uint64_t ol_flags;
|
||||
struct rte_mbuf *m;
|
||||
|
||||
for (i = 0; i < nb_pkts; i++) {
|
||||
m = tx_pkts[i];
|
||||
ol_flags = m->ol_flags;
|
||||
|
||||
if (ol_flags & PKT_TX_TCP_SEG &&
|
||||
(m->tso_segsz < ICE_MIN_TSO_MSS ||
|
||||
m->tso_segsz > ICE_MAX_TSO_MSS ||
|
||||
m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
|
||||
/**
|
||||
* MSS outside the range are considered malicious
|
||||
*/
|
||||
rte_errno = -EINVAL;
|
||||
return i;
|
||||
}
|
||||
|
||||
#ifdef RTE_LIBRTE_ETHDEV_DEBUG
|
||||
ret = rte_validate_tx_offload(m);
|
||||
if (ret != 0) {
|
||||
rte_errno = ret;
|
||||
return i;
|
||||
}
|
||||
#endif
|
||||
ret = rte_net_intel_cksum_prepare(m);
|
||||
if (ret != 0) {
|
||||
rte_errno = ret;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
void __attribute__((cold))
|
||||
ice_set_tx_function(struct rte_eth_dev *dev)
|
||||
{
|
||||
dev->tx_pkt_burst = ice_xmit_pkts;
|
||||
dev->tx_pkt_prepare = ice_prep_pkts;
|
||||
}
|
||||
|
||||
/* For each value it means, datasheet of hardware can tell more details
|
||||
*
|
||||
* @note: fix ice_dev_supported_ptypes_get() if any change here.
|
||||
|
||||
@ -134,6 +134,14 @@ void ice_rx_queue_release(void *rxq);
|
||||
void ice_tx_queue_release(void *txq);
|
||||
void ice_clear_queues(struct rte_eth_dev *dev);
|
||||
void ice_free_queues(struct rte_eth_dev *dev);
|
||||
uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
|
||||
uint16_t nb_pkts);
|
||||
uint16_t ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t nb_pkts);
|
||||
void ice_set_rx_function(struct rte_eth_dev *dev);
|
||||
uint16_t ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
|
||||
uint16_t nb_pkts);
|
||||
void ice_set_tx_function(struct rte_eth_dev *dev);
|
||||
uint32_t ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
|
||||
void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
|
||||
struct rte_eth_rxq_info *qinfo);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user