raw/octeontx2_dma: add build infra and device probe
Add the make and meson based build infrastructure along with the DMA device probe with documentation infrastructure. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Satha Rao <skoteshwar@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
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@ -1105,6 +1105,12 @@ M: Nipun Gupta <nipun.gupta@nxp.com>
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F: drivers/raw/dpaa2_cmdif/
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F: doc/guides/rawdevs/dpaa2_cmdif.rst
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Marvell OCTEON TX2 DMA
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M: Satha Rao <skoteshwar@marvell.com>
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M: Vamsi Attunuru <vattunuru@marvell.com>
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F: drivers/raw/octeontx2_dma/
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F: doc/guides/rawdevs/octeontx2_dma.rst
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Packet processing
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-----------------
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@ -762,6 +762,11 @@ CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y
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#
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CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV=y
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#
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# Compile PMD for octeontx2 DMA raw device
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#
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CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV=y
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#
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# Compile librte_ring
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#
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@ -104,6 +104,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.
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#. **Event Device Driver**
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See :doc:`../eventdevs/octeontx2` for SSO event device driver information.
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#. **DMA Rawdev Driver**
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See :doc:`../rawdevs/octeontx2_dma` for DMA driver information.
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Procedure to Setup Platform
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---------------------------
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@ -146,6 +149,8 @@ compatible board:
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# Enable if netdev VF driver required
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CONFIG_OCTEONTX2_VF=y
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CONFIG_CRYPTO_DEV_OCTEONTX2_CPT=y
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# Enable if OCTEONTX2 DMA PF driver required
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CONFIG_OCTEONTX2_DPI_PF=n
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2. **ARM64 Linux Tool Chain**
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@ -15,3 +15,4 @@ application through rawdev API.
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dpaa2_qdma
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ifpga_rawdev
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ioat_rawdev
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octeontx2_dma
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64
doc/guides/rawdevs/octeontx2_dma.rst
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64
doc/guides/rawdevs/octeontx2_dma.rst
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@ -0,0 +1,64 @@
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.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(c) 2019 Marvell International Ltd.
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OCTEON TX2 DMA Driver
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=====================
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OCTEON TX2 has an internal DMA unit which can be used by applications to initiate
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DMA transaction internally, from/to host when OCTEON TX2 operates in PCIe End
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Point mode. The DMA PF function supports 8 VFs corresponding to 8 DMA queues.
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Each DMA queue was exposed as a VF function when SRIOV enabled.
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Features
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--------
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This DMA PMD supports below 3 modes of memory transfers
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#. Internal - OCTEON TX2 DRAM to DRAM without core intervention
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#. Inbound - Host DRAM to OCTEON TX2 DRAM without host/OCTEON TX2 cores involvement
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#. Outbound - OCTEON TX2 DRAM to Host DRAM without host/OCTEON TX2 cores involvement
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Prerequisites and Compilation procedure
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---------------------------------------
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See :doc:`../platform/octeontx2` for setup information.
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Pre-Installation Configuration
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------------------------------
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Config File Options
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~~~~~~~~~~~~~~~~~~~
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The following options can be modified in the ``config`` file.
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- ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV`` (default ``y``)
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Toggle compilation of the ``lrte_pmd_octeontx2_dma`` driver.
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Enabling logs
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-------------
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For enabling logs, use the following EAL parameter:
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.. code-block:: console
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./your_dma_application <EAL args> --log-level=pmd.raw.octeontx2.dpi,<level>
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Using ``pmd.raw.octeontx2.dpi`` as log matching criteria, all Event PMD logs
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can be enabled which are lower than logging ``level``.
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Initialization
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--------------
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The number of DMA VFs (queues) enabled can be controlled by setting sysfs
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entry, `sriov_numvfs` for the corresponding PF driver.
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.. code-block:: console
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echo <num_vfs> > /sys/bus/pci/drivers/octeontx2-dpi/0000\:05\:00.0/sriov_numvfs
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Once the required VFs are enabled, to be accessible from DPDK, VFs need to be
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bound to vfio-pci driver.
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@ -11,5 +11,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV) += dpaa2_qdma
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endif
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DIRS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += ifpga_rawdev
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DIRS-$(CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV) += ioat
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DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += octeontx2_dma
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include $(RTE_SDK)/mk/rte.subdir.mk
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@ -3,6 +3,7 @@
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drivers = ['dpaa2_cmdif', 'dpaa2_qdma',
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'ifpga_rawdev', 'ioat',
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'octeontx2_dma',
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'skeleton_rawdev']
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std_deps = ['rawdev']
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config_flag_fmt = 'RTE_LIBRTE_PMD_@0@_RAWDEV'
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25
drivers/raw/octeontx2_dma/Makefile
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25
drivers/raw/octeontx2_dma/Makefile
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@ -0,0 +1,25 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(C) 2019 Marvell International Ltd.
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#
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include $(RTE_SDK)/mk/rte.vars.mk
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# library name
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LIB = librte_pmd_octeontx2_dma.a
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CFLAGS += -O3 $(WERROR_FLAGS)
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CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2/
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CFLAGS += -I$(RTE_SDK)/drivers/raw/octeontx2_dma/
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LDLIBS += -lrte_eal -lrte_rawdev -lrte_bus_pci
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LDLIBS += -lrte_common_octeontx2
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EXPORT_MAP := rte_pmd_octeontx2_dma_version.map
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LIBABIVER := 1
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#
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# all source are stored in SRCS-y
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#
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SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += otx2_dpi_rawdev.c
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include $(RTE_SDK)/mk/rte.lib.mk
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6
drivers/raw/octeontx2_dma/meson.build
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6
drivers/raw/octeontx2_dma/meson.build
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(C) 2019 Marvell International Ltd.
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#
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deps += ['bus_pci', 'common_octeontx2', 'rawdev']
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sources = files('otx2_dpi_rawdev.c')
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99
drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
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99
drivers/raw/octeontx2_dma/otx2_dpi_rawdev.c
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@ -0,0 +1,99 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <string.h>
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#include <unistd.h>
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#include <rte_bus.h>
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#include <rte_bus_pci.h>
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#include <rte_common.h>
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#include <rte_eal.h>
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#include <rte_lcore.h>
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#include <rte_pci.h>
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#include <rte_rawdev.h>
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#include <rte_rawdev_pmd.h>
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#include <otx2_common.h>
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static const struct rte_pci_id pci_dma_map[] = {
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{
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RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVID_OCTEONTX2_DPI_VF)
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},
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{
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.vendor_id = 0,
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},
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};
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static int
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otx2_dpi_rawdev_probe(struct rte_pci_driver *pci_drv __rte_unused,
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struct rte_pci_device *pci_dev)
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{
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char name[RTE_RAWDEV_NAME_MAX_LEN];
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struct rte_rawdev *rawdev;
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/* For secondary processes, the primary has done all the work */
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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if (pci_dev->mem_resource[0].addr == NULL) {
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otx2_dpi_dbg("Empty bars %p %p", pci_dev->mem_resource[0].addr,
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pci_dev->mem_resource[2].addr);
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return -ENODEV;
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}
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memset(name, 0, sizeof(name));
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snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
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pci_dev->addr.bus, pci_dev->addr.devid,
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pci_dev->addr.function);
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/* Allocate device structure */
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rawdev = rte_rawdev_pmd_allocate(name, 0, rte_socket_id());
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if (rawdev == NULL) {
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otx2_err("Rawdev allocation failed");
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return -EINVAL;
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}
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rawdev->device = &pci_dev->device;
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rawdev->driver_name = pci_dev->driver->driver.name;
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return 0;
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}
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static int
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otx2_dpi_rawdev_remove(struct rte_pci_device *pci_dev)
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{
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char name[RTE_RAWDEV_NAME_MAX_LEN];
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struct rte_rawdev *rawdev;
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if (pci_dev == NULL) {
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otx2_dpi_dbg("Invalid pci_dev of the device!");
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return -EINVAL;
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}
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memset(name, 0, sizeof(name));
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snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "DPI:%x:%02x.%x",
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pci_dev->addr.bus, pci_dev->addr.devid,
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pci_dev->addr.function);
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rawdev = rte_rawdev_pmd_get_named_dev(name);
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if (rawdev == NULL) {
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otx2_dpi_dbg("Invalid device name (%s)", name);
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return -EINVAL;
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}
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/* rte_rawdev_close is called by pmd_release */
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return rte_rawdev_pmd_release(rawdev);
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}
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static struct rte_pci_driver rte_dpi_rawdev_pmd = {
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.id_table = pci_dma_map,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
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.probe = otx2_dpi_rawdev_probe,
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.remove = otx2_dpi_rawdev_remove,
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};
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RTE_PMD_REGISTER_PCI(dpi_rawdev_pci_driver, rte_dpi_rawdev_pmd);
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RTE_PMD_REGISTER_PCI_TABLE(dpi_rawdev_pci_driver, pci_dma_map);
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RTE_PMD_REGISTER_KMOD_DEP(dpi_rawdev_pci_driver, "vfio-pci");
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DPDK_19.08 {
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local: *;
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};
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@ -110,6 +110,7 @@ _LDLIBS-y += -lrte_common_octeontx
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endif
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OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
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OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)
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OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV)
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ifeq ($(findstring y,$(OCTEONTX2-y)),y)
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_LDLIBS-y += -lrte_common_octeontx2
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endif
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@ -310,6 +311,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV) += -lrte_pmd_ifpga_rawdev
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_LDLIBS-$(CONFIG_RTE_LIBRTE_IPN3KE_PMD) += -lrte_pmd_ipn3ke
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endif # CONFIG_RTE_LIBRTE_IFPGA_BUS
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_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV) += -lrte_pmd_ioat_rawdev
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_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV) += -lrte_pmd_octeontx2_dma
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endif # CONFIG_RTE_LIBRTE_RAWDEV
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endif # !CONFIG_RTE_BUILD_SHARED_LIBS
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