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eal/ppc: fix prefetch instruction

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Current prefetch instruction (dcbt) implementation for IBM POWER8 has wrong
Touch Hint(TH) parameter. The current setting of TH=1 indicates to load data from
current cache line and an unlimited number of sequentially following cache lines.
TTH=0 means to load data from current cache line. rte_prefetch0 function is defined
to load one cache line, which means TH=0 is suited here.

Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
This commit is contained in:
Chao Zhu 2016-03-30 23:39:17 +08:00 committed by Thomas Monjalon
parent a88ba49e51
commit 1861116ee6
1 changed files with 3 additions and 3 deletions
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6
lib/librte_eal/common/include/arch/ppc_64/rte_prefetch.h
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@ -41,17 +41,17 @@ extern "C" {
static inline void rte_prefetch0(const volatile void *p)
{
asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
}
static inline void rte_prefetch1(const volatile void *p)
{
asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
}
static inline void rte_prefetch2(const volatile void *p)
{
asm volatile ("dcbt 0,%[p],1" : : [p] "r" (p));
asm volatile ("dcbt 0,%[p],0" : : [p] "r" (p));
}
static inline void rte_prefetch_non_temporal(const volatile void *p)