net/i40e: fix shifts of signed values
Following error reported by cppcheck:
(error) Shifting signed 32-bit value by 31 bits is
undefined behaviour. The patch fixes it.
Fixes: 8db9e2a1b2
("i40e: base driver")
Cc: stable@dpdk.org
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This commit is contained in:
parent
4ebbe84dae
commit
1962193cc8
@ -90,7 +90,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
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#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)
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#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
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#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
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#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT)
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#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */
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#define I40E_PF_ARQT_ARQT_SHIFT 0
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#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)
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@ -113,7 +113,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
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#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)
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#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
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#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
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#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT)
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#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */
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#define I40E_PF_ATQT_ATQT_SHIFT 0
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#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)
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@ -140,7 +140,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30
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#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)
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#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
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#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
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#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN_ARQENABLE_SHIFT)
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#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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#define I40E_VF_ARQT_MAX_INDEX 127
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#define I40E_VF_ARQT_ARQT_SHIFT 0
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@ -168,7 +168,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30
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#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)
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#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
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#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
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#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN_ATQENABLE_SHIFT)
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#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */
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#define I40E_VF_ATQT_MAX_INDEX 127
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#define I40E_VF_ATQT_ATQT_SHIFT 0
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@ -291,7 +291,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
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#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
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#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
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#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
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#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
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#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */
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#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
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#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
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@ -535,7 +535,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
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#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)
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#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
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#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
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#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
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#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */
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#define I40E_GLGEN_MSRWD_MAX_INDEX 3
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#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
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@ -1274,14 +1274,14 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30
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#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)
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#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31
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#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
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#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)
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#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */
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#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
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#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
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#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
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#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)
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#define I40E_PFLAN_QALLOC_VALID_SHIFT 31
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#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)
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#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT)
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#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */
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#define I40E_QRX_ENA_MAX_INDEX 1535
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#define I40E_QRX_ENA_QENA_REQ_SHIFT 0
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@ -1692,7 +1692,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_GLNVM_SRCTL_START_SHIFT 30
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#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)
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#define I40E_GLNVM_SRCTL_DONE_SHIFT 31
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#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)
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#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT)
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#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */
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#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
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#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)
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@ -3059,7 +3059,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
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#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
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#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
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#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)
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#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT)
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#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */
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#define I40E_VP_MDET_RX_MAX_INDEX 127
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#define I40E_VP_MDET_RX_VALID_SHIFT 0
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@ -3196,7 +3196,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
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#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
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#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
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#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
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#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
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#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
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#define I40E_VF_ARQT1_ARQT_SHIFT 0
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#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
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@ -3219,7 +3219,7 @@ POSSIBILITY OF SUCH DAMAGE.
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#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
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#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
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#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
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#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
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#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
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#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
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#define I40E_VF_ATQT1_ATQT_SHIFT 0
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#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
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