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net/sfc/base: clarify port mode names and masks

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New port mode names are defined for Medford2 and later, and
the existing names are aliased to them. Add comments with the
numeric port mode to clarify the external port modes table.

Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
This commit is contained in:
Andy Moreton 2018-02-20 07:34:21 +00:00 committed by Ferruh Yigit
parent 75ff34e83e
commit 1a04c2d163
2 changed files with 34 additions and 32 deletions
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60
drivers/net/sfc/base/ef10_nic.c
View File

@ -1345,11 +1345,11 @@ static struct ef10_external_port_map_s {
*/
{
EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_10G) |
(1 << TLV_PORT_MODE_10G_10G) |
(1 << TLV_PORT_MODE_10G_10G_10G_10G),
1,
1
(1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1U << TLV_PORT_MODE_10G_10G) | /* mode 2 */
(1U << TLV_PORT_MODE_10G_10G_10G_10G), /* mode 4 */
1, /* ports per cage */
1 /* first cage */
},
/*
* Modes that on Medford allocate each port number to a separate
@ -1361,10 +1361,10 @@ static struct ef10_external_port_map_s {
*/
{
EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G) |
(1 << TLV_PORT_MODE_10G_10G),
1,
1
(1U << TLV_PORT_MODE_10G) | /* mode 0 */
(1U << TLV_PORT_MODE_10G_10G), /* mode 2 */
1, /* ports per cage */
1 /* first cage */
},
/*
* Modes which for Huntington identify a chip variant where 2
@ -1377,12 +1377,12 @@ static struct ef10_external_port_map_s {
*/
{
EFX_FAMILY_HUNTINGTON,
(1 << TLV_PORT_MODE_40G) |
(1 << TLV_PORT_MODE_40G_40G) |
(1 << TLV_PORT_MODE_40G_10G_10G) |
(1 << TLV_PORT_MODE_10G_10G_40G),
2,
1
(1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1U << TLV_PORT_MODE_10G_10G_40G), /* mode 7 */
2, /* ports per cage */
1 /* first cage */
},
/*
* Modes that on Medford allocate 2 adjacent port numbers to each
@ -1394,13 +1394,14 @@ static struct ef10_external_port_map_s {
*/
{
EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_40G) |
(1 << TLV_PORT_MODE_40G_40G) |
(1 << TLV_PORT_MODE_40G_10G_10G) |
(1 << TLV_PORT_MODE_10G_10G_40G) |
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2),
2,
1
(1U << TLV_PORT_MODE_40G) | /* mode 1 */
(1U << TLV_PORT_MODE_40G_40G) | /* mode 3 */
(1U << TLV_PORT_MODE_40G_10G_10G) | /* mode 6 */
(1U << TLV_PORT_MODE_10G_10G_40G) | /* mode 7 */
/* Do not use 10G_10G_10G_10G_Q1_Q2 (see bug63270) */
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2), /* mode 9 */
2, /* ports per cage */
1 /* first cage */
},
/*
* Modes that on Medford allocate 4 adjacent port numbers to each
@ -1412,10 +1413,11 @@ static struct ef10_external_port_map_s {
*/
{
EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q1),
4,
1,
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q) | /* mode 5 */
/* Do not use 10G_10G_10G_10G_Q1 (see bug63270) */
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q1), /* mode 4 */
4, /* ports per cage */
1 /* first cage */
},
/*
* Modes that on Medford allocate 4 adjacent port numbers to each
@ -1427,9 +1429,9 @@ static struct ef10_external_port_map_s {
*/
{
EFX_FAMILY_MEDFORD,
(1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
4,
2
(1U << TLV_PORT_MODE_10G_10G_10G_10G_Q2), /* mode 8 */
4, /* ports per cage */
2 /* first cage */
},
};

6
drivers/net/sfc/base/hunt_nic.c
View File

@ -36,7 +36,7 @@ hunt_nic_get_required_pcie_bandwidth(
goto out;
}
if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
/*
* This needs the full PCIe bandwidth (and could use
* more) - roughly 64 Gbit/s for 8 lanes of Gen3.
@ -45,9 +45,9 @@ hunt_nic_get_required_pcie_bandwidth(
EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
goto fail1;
} else {
if (port_modes & (1 << TLV_PORT_MODE_40G)) {
if (port_modes & (1U << TLV_PORT_MODE_40G)) {
max_port_mode = TLV_PORT_MODE_40G;
} else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
} else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
} else {
/* Assume two 10G ports */