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net/ionic: remove some unused fields

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This conserves resources.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Andrew Boyer 2020-12-09 18:57:33 -08:00 committed by Ferruh Yigit
parent 47dc2bd39f
commit 1abf69fc26
7 changed files with 8 additions and 37 deletions
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1
drivers/net/ionic/ionic.h
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@ -59,7 +59,6 @@ struct ionic_adapter {
uint32_t link_speed;
uint32_t nintrs;
bool intrs[IONIC_INTR_CTRL_REGS_MAX];
bool is_mgmt_nic;
bool link_up;
char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
struct rte_pci_device *pci_dev;

5
drivers/net/ionic/ionic_dev.c
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@ -65,7 +65,6 @@ ionic_dev_setup(struct ionic_adapter *adapter)
}
idev->db_pages = bar->vaddr;
idev->phy_db_pages = bar->bus_addr;
return 0;
}
@ -343,7 +342,6 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev,
.q_init.type = q->type,
.q_init.index = q->index,
.q_init.flags = IONIC_QINIT_F_ENA,
.q_init.pid = q->pid,
.q_init.intr_index = intr_index,
.q_init.ring_size = rte_log2_u32(q->num_descs),
.q_init.ring_base = q->base_pa,
@ -419,7 +417,7 @@ ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
int
ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
struct ionic_queue *q, uint32_t index, uint32_t num_descs,
size_t desc_size, size_t sg_desc_size, uint32_t pid)
size_t desc_size, size_t sg_desc_size)
{
uint32_t ring_size;
@ -439,7 +437,6 @@ ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
q->sg_desc_size = sg_desc_size;
q->head_idx = 0;
q->tail_idx = 0;
q->pid = pid;
return 0;
}

7
drivers/net/ionic/ionic_dev.h
View File

@ -120,10 +120,7 @@ struct ionic_dev {
union ionic_dev_cmd_regs __iomem *dev_cmd;
struct ionic_doorbell __iomem *db_pages;
rte_iova_t phy_db_pages;
struct ionic_intr __iomem *intr_ctrl;
struct ionic_intr_status __iomem *intr_status;
struct ionic_port_info *port_info;
@ -163,11 +160,9 @@ struct ionic_queue {
uint32_t num_descs;
uint32_t desc_size;
uint32_t sg_desc_size;
uint32_t pid;
uint32_t qid;
uint32_t qtype;
struct ionic_doorbell __iomem *db;
void *nop_desc;
};
#define IONIC_INTR_INDEX_NOT_ASSIGNED (-1)
@ -257,7 +252,7 @@ uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
struct ionic_queue *q, uint32_t index, uint32_t num_descs,
size_t desc_size, size_t sg_desc_size, uint32_t pid);
size_t desc_size, size_t sg_desc_size);
void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa);
void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa);
void ionic_q_flush(struct ionic_queue *q);

2
drivers/net/ionic/ionic_ethdev.c
View File

@ -1178,8 +1178,6 @@ eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
goto err_free_adapter;
}
adapter->is_mgmt_nic = (pci_dev->id.device_id == IONIC_DEV_ID_ETH_MGMT);
adapter->num_bars = 0;
for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) {
resource = &pci_dev->mem_resource[i];

22
drivers/net/ionic/ionic_lif.c
View File

@ -536,8 +536,6 @@ ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu)
if (err)
return err;
lif->mtu = new_mtu;
return 0;
}
@ -583,7 +581,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
uint32_t desc_size,
uint32_t cq_desc_size,
uint32_t sg_desc_size,
uint32_t pid, struct ionic_qcq **qcq)
struct ionic_qcq **qcq)
{
struct ionic_dev *idev = &lif->adapter->idev;
struct ionic_qcq *new;
@ -633,7 +631,7 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
new->q.type = type;
err = ionic_q_init(lif, idev, &new->q, index, num_descs,
desc_size, sg_desc_size, pid);
desc_size, sg_desc_size);
if (err) {
IONIC_PRINT(ERR, "Queue initialization failed");
return err;
@ -734,7 +732,7 @@ ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t nrxq_descs,
sizeof(struct ionic_rxq_desc),
sizeof(struct ionic_rxq_comp),
sizeof(struct ionic_rxq_sg_desc),
lif->kern_pid, &lif->rxqcqs[index]);
&lif->rxqcqs[index]);
if (err)
return err;
@ -756,7 +754,7 @@ ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t index, uint16_t ntxq_descs,
sizeof(struct ionic_txq_desc),
sizeof(struct ionic_txq_comp),
sizeof(struct ionic_txq_sg_desc),
lif->kern_pid, &lif->txqcqs[index]);
&lif->txqcqs[index]);
if (err)
return err;
@ -777,7 +775,7 @@ ionic_admin_qcq_alloc(struct ionic_lif *lif)
sizeof(struct ionic_admin_cmd),
sizeof(struct ionic_admin_comp),
0,
lif->kern_pid, &lif->adminqcq);
&lif->adminqcq);
if (err)
return err;
@ -798,7 +796,7 @@ ionic_notify_qcq_alloc(struct ionic_lif *lif)
sizeof(struct ionic_notifyq_cmd),
sizeof(union ionic_notifyq_comp),
0,
lif->kern_pid, &lif->notifyqcq);
&lif->notifyqcq);
if (err)
return err;
@ -831,8 +829,6 @@ ionic_lif_alloc(struct ionic_lif *lif)
rte_spinlock_init(&lif->adminq_lock);
rte_spinlock_init(&lif->adminq_service_lock);
lif->kern_pid = 0;
dbpage_num = ionic_db_page_num(lif, 0);
lif->kern_dbpage = ionic_bus_map_dbpage(adapter, dbpage_num);
@ -1211,13 +1207,11 @@ ionic_lif_notifyq_init(struct ionic_lif *lif)
.index = q->index,
.flags = (IONIC_QINIT_F_IRQ | IONIC_QINIT_F_ENA),
.intr_index = qcq->intr.index,
.pid = q->pid,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
}
};
IONIC_PRINT(DEBUG, "notifyq_init.pid %d", ctx.cmd.q_init.pid);
IONIC_PRINT(DEBUG, "notifyq_init.index %d",
ctx.cmd.q_init.index);
IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "",
@ -1320,7 +1314,6 @@ ionic_lif_txq_init(struct ionic_qcq *qcq)
.index = q->index,
.flags = IONIC_QINIT_F_SG,
.intr_index = cq->bound_intr->index,
.pid = q->pid,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
.cq_ring_base = cq->base_pa,
@ -1329,7 +1322,6 @@ ionic_lif_txq_init(struct ionic_qcq *qcq)
};
int err;
IONIC_PRINT(DEBUG, "txq_init.pid %d", ctx.cmd.q_init.pid);
IONIC_PRINT(DEBUG, "txq_init.index %d", ctx.cmd.q_init.index);
IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "",
ctx.cmd.q_init.ring_base);
@ -1368,7 +1360,6 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq)
.index = q->index,
.flags = IONIC_QINIT_F_SG,
.intr_index = cq->bound_intr->index,
.pid = q->pid,
.ring_size = rte_log2_u32(q->num_descs),
.ring_base = q->base_pa,
.cq_ring_base = cq->base_pa,
@ -1377,7 +1368,6 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq)
};
int err;
IONIC_PRINT(DEBUG, "rxq_init.pid %d", ctx.cmd.q_init.pid);
IONIC_PRINT(DEBUG, "rxq_init.index %d", ctx.cmd.q_init.index);
IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "",
ctx.cmd.q_init.ring_base);

2
drivers/net/ionic/ionic_lif.h
View File

@ -84,13 +84,11 @@ struct ionic_lif {
struct ionic_adapter *adapter;
struct rte_eth_dev *eth_dev;
uint16_t port_id; /**< Device port identifier */
uint16_t mtu;
uint32_t index;
uint32_t hw_index;
uint32_t state;
uint32_t ntxqcqs;
uint32_t nrxqcqs;
uint32_t kern_pid;
rte_spinlock_t adminq_lock;
rte_spinlock_t adminq_service_lock;
struct ionic_qcq *adminqcq;

6
drivers/net/ionic/ionic_regs.h
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@ -130,10 +130,4 @@ enum ionic_dbell_bits {
IONIC_DBELL_INDEX_MASK = 0xffff,
};
static inline void
ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val)
{
writeq(val, &db_page[qtype]);
}
#endif /* _IONIC_REGS_H_ */