ixgbe/base: allow to read in sff8472
Signed-off-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com> [Thomas: split code drop]
This commit is contained in:
Jijiang Liu
Thomas Monjalon
parent
e7012e2c22
commit
1acad5657a
@ -65,7 +65,8 @@ STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
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STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
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STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
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u32 headroom, int strategy);
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STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *sff8472_data);
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/**
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* ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
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* @hw: pointer to the HW structure
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@ -161,6 +162,7 @@ s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
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/* SFP+ Module */
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phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
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phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598;
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/* Link */
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mac->ops.check_link = &ixgbe_check_mac_link_82598;
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@ -1108,15 +1110,16 @@ s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
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}
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/**
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* ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
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* ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
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* @hw: pointer to hardware structure
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* @byte_offset: EEPROM byte offset to read
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* @dev_addr: address to read from
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* @byte_offset: byte offset to read from dev_addr
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* @eeprom_data: value read
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*
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* Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
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**/
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s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *eeprom_data)
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STATIC s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
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u8 byte_offset, u8 *eeprom_data)
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{
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s32 status = IXGBE_SUCCESS;
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u16 sfp_addr = 0;
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@ -1125,7 +1128,7 @@ s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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u16 gssr;
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u32 i;
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DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
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DEBUGFUNC("ixgbe_read_i2c_phy_82598");
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if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
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gssr = IXGBE_GSSR_PHY1_SM;
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@ -1141,19 +1144,19 @@ s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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* 0xC30D. These registers are used to talk to the SFP+
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* module's EEPROM through the SDA/SCL (I2C) interface.
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*/
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sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
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sfp_addr = (dev_addr << 8) + byte_offset;
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sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
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hw->phy.ops.write_reg(hw,
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IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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sfp_addr);
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hw->phy.ops.write_reg_mdi(hw,
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IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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sfp_addr);
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/* Poll status */
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for (i = 0; i < 100; i++) {
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hw->phy.ops.read_reg(hw,
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IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&sfp_stat);
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hw->phy.ops.read_reg_mdi(hw,
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IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE,
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&sfp_stat);
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sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
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if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
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break;
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@ -1167,13 +1170,12 @@ s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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}
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/* Read data */
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hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
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hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
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IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
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*eeprom_data = (u8)(sfp_data >> 8);
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} else {
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status = IXGBE_ERR_PHY;
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goto out;
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}
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out:
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@ -1181,6 +1183,36 @@ out:
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return status;
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}
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/**
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* ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
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* @hw: pointer to hardware structure
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* @byte_offset: EEPROM byte offset to read
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* @eeprom_data: value read
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*
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* Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
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**/
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s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *eeprom_data)
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{
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return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
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byte_offset, eeprom_data);
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}
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/**
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* ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset at address 0xA2
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* @eeprom_data: value read
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*
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* Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
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**/
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STATIC s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *sff8472_data)
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{
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return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
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byte_offset, sff8472_data);
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}
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/**
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* ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
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* @hw: pointer to hardware structure
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@ -47,6 +47,8 @@ STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
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STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
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STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
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STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
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STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *sff8472_data);
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/**
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* ixgbe_init_phy_ops_generic - Inits PHY function ptrs
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@ -73,6 +75,7 @@ s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
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phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
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phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
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phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
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phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
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phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
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phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
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phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
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@ -1461,6 +1464,22 @@ s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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eeprom_data);
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}
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/**
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* ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
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* @hw: pointer to hardware structure
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* @byte_offset: byte offset at address 0xA2
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* @eeprom_data: value read
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*
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* Performs byte read operation to SFP module's SFF-8472 data over I2C
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**/
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STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *sff8472_data)
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{
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return hw->phy.ops.read_i2c_byte(hw, byte_offset,
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IXGBE_I2C_EEPROM_DEV_ADDR2,
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sff8472_data);
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}
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/**
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* ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
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* @hw: pointer to hardware structure
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@ -35,7 +35,9 @@ POSSIBILITY OF SUCH DAMAGE.
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#define _IXGBE_PHY_H_
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#include "ixgbe_type.h"
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#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
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#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
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#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
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#define IXGBE_I2C_EEPROM_BANK_LEN 0xFF
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/* EEPROM byte offsets */
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#define IXGBE_SFF_IDENTIFIER 0x0
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@ -47,6 +49,8 @@ POSSIBILITY OF SUCH DAMAGE.
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#define IXGBE_SFF_10GBE_COMP_CODES 0x3
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#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
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#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
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#define IXGBE_SFF_SFF_8472_SWAP 0x5C
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#define IXGBE_SFF_SFF_8472_COMP 0x5E
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/* Bitmasks */
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#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
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@ -98,6 +102,9 @@ POSSIBILITY OF SUCH DAMAGE.
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#define IXGBE_TN_LASI_STATUS_REG 0x9005
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#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
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/* SFP+ SFF-8472 Compliance */
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#define IXGBE_SFF_SFF_8472_UNSUP 0x00
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#ident "$Id: ixgbe_phy.h,v 1.48 2012/01/04 01:49:02 jtkirshe Exp $"
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s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
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@ -3115,6 +3115,7 @@ struct ixgbe_phy_operations {
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s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
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s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
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s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
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s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
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s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
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s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
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void (*i2c_bus_clear)(struct ixgbe_hw *);
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