net/octeontx2: add Tx queue setup and release
Add Tx queue setup and release. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This commit is contained in:
Jerin Jacob
Ferruh Yigit
parent
094fc8a3a1
commit
1be5cff1fa
@ -11,6 +11,7 @@ Multiprocess aware = Y
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Link status = Y
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Link status event = Y
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Runtime Rx queue setup = Y
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Runtime Tx queue setup = Y
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Promiscuous mode = Y
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Allmulticast mode = Y
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Unicast MAC filter = Y
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@ -11,6 +11,7 @@ Multiprocess aware = Y
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Link status = Y
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Link status event = Y
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Runtime Rx queue setup = Y
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Runtime Tx queue setup = Y
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Promiscuous mode = Y
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Allmulticast mode = Y
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Unicast MAC filter = Y
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@ -10,6 +10,7 @@ Multiprocess aware = Y
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Link status = Y
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Link status event = Y
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Runtime Rx queue setup = Y
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Runtime Tx queue setup = Y
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RSS hash = Y
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RSS key update = Y
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RSS reta update = Y
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@ -19,6 +19,7 @@ Features of the OCTEON TX2 Ethdev PMD are:
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- Promiscuous mode
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- SR-IOV VF
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- Lock-free Tx queue
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- Multiple queues for TX and RX
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- Receiver Side Scaling (RSS)
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- MAC filtering
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- Port hardware statistics
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@ -422,6 +422,392 @@ fail:
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return rc;
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}
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static inline uint8_t
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nix_sq_max_sqe_sz(struct otx2_eth_txq *txq)
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{
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/*
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* Maximum three segments can be supported with W8, Choose
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* NIX_MAXSQESZ_W16 for multi segment offload.
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*/
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if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
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return NIX_MAXSQESZ_W16;
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else
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return NIX_MAXSQESZ_W8;
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}
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static int
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nix_sq_init(struct otx2_eth_txq *txq)
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{
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struct otx2_eth_dev *dev = txq->dev;
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struct otx2_mbox *mbox = dev->mbox;
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struct nix_aq_enq_req *sq;
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if (txq->sqb_pool->pool_id == 0)
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return -EINVAL;
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sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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sq->qidx = txq->sq;
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sq->ctype = NIX_AQ_CTYPE_SQ;
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sq->op = NIX_AQ_INSTOP_INIT;
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sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
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sq->sq.default_chan = dev->tx_chan_base;
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sq->sq.sqe_stype = NIX_STYPE_STF;
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sq->sq.ena = 1;
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if (sq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
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sq->sq.sqe_stype = NIX_STYPE_STP;
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sq->sq.sqb_aura =
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npa_lf_aura_handle_to_aura(txq->sqb_pool->pool_id);
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sq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
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sq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
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sq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
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sq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
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/* Many to one reduction */
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sq->sq.qint_idx = txq->sq % dev->qints;
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return otx2_mbox_process(mbox);
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}
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static int
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nix_sq_uninit(struct otx2_eth_txq *txq)
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{
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struct otx2_eth_dev *dev = txq->dev;
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struct otx2_mbox *mbox = dev->mbox;
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struct ndc_sync_op *ndc_req;
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struct nix_aq_enq_rsp *rsp;
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struct nix_aq_enq_req *aq;
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uint16_t sqes_per_sqb;
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void *sqb_buf;
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int rc, count;
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otx2_nix_dbg("Cleaning up sq %u", txq->sq);
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aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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aq->qidx = txq->sq;
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aq->ctype = NIX_AQ_CTYPE_SQ;
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aq->op = NIX_AQ_INSTOP_READ;
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rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
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if (rc)
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return rc;
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/* Check if sq is already cleaned up */
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if (!rsp->sq.ena)
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return 0;
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/* Disable sq */
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aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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aq->qidx = txq->sq;
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aq->ctype = NIX_AQ_CTYPE_SQ;
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aq->op = NIX_AQ_INSTOP_WRITE;
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aq->sq_mask.ena = ~aq->sq_mask.ena;
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aq->sq.ena = 0;
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rc = otx2_mbox_process(mbox);
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if (rc)
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return rc;
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/* Read SQ and free sqb's */
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aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
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aq->qidx = txq->sq;
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aq->ctype = NIX_AQ_CTYPE_SQ;
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aq->op = NIX_AQ_INSTOP_READ;
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rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
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if (rc)
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return rc;
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if (aq->sq.smq_pend)
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otx2_err("SQ has pending sqe's");
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count = aq->sq.sqb_count;
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sqes_per_sqb = 1 << txq->sqes_per_sqb_log2;
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/* Free SQB's that are used */
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sqb_buf = (void *)rsp->sq.head_sqb;
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while (count) {
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void *next_sqb;
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next_sqb = *(void **)((uintptr_t)sqb_buf + ((sqes_per_sqb - 1) *
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nix_sq_max_sqe_sz(txq)));
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npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
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(uint64_t)sqb_buf);
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sqb_buf = next_sqb;
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count--;
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}
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/* Free next to use sqb */
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if (rsp->sq.next_sqb)
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npa_lf_aura_op_free(txq->sqb_pool->pool_id, 1,
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rsp->sq.next_sqb);
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/* Sync NDC-NIX-TX for LF */
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ndc_req = otx2_mbox_alloc_msg_ndc_sync_op(mbox);
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ndc_req->nix_lf_tx_sync = 1;
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rc = otx2_mbox_process(mbox);
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if (rc)
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otx2_err("Error on NDC-NIX-TX LF sync, rc %d", rc);
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return rc;
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}
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static int
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nix_sqb_aura_limit_cfg(struct rte_mempool *mp, uint16_t nb_sqb_bufs)
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{
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struct otx2_npa_lf *npa_lf = otx2_intra_dev_get_cfg()->npa_lf;
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struct npa_aq_enq_req *aura_req;
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aura_req = otx2_mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
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aura_req->aura_id = npa_lf_aura_handle_to_aura(mp->pool_id);
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aura_req->ctype = NPA_AQ_CTYPE_AURA;
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aura_req->op = NPA_AQ_INSTOP_WRITE;
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aura_req->aura.limit = nb_sqb_bufs;
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aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
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return otx2_mbox_process(npa_lf->mbox);
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}
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static int
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nix_alloc_sqb_pool(int port, struct otx2_eth_txq *txq, uint16_t nb_desc)
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{
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struct otx2_eth_dev *dev = txq->dev;
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uint16_t sqes_per_sqb, nb_sqb_bufs;
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char name[RTE_MEMPOOL_NAMESIZE];
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struct rte_mempool_objsz sz;
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struct npa_aura_s *aura;
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uint32_t tmp, blk_sz;
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aura = (struct npa_aura_s *)((uintptr_t)txq->fc_mem + OTX2_ALIGN);
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snprintf(name, sizeof(name), "otx2_sqb_pool_%d_%d", port, txq->sq);
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blk_sz = dev->sqb_size;
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if (nix_sq_max_sqe_sz(txq) == NIX_MAXSQESZ_W16)
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sqes_per_sqb = (dev->sqb_size / 8) / 16;
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else
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sqes_per_sqb = (dev->sqb_size / 8) / 8;
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nb_sqb_bufs = nb_desc / sqes_per_sqb;
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/* Clamp up to devarg passed SQB count */
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nb_sqb_bufs = RTE_MIN(dev->max_sqb_count, RTE_MAX(NIX_MIN_SQB,
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nb_sqb_bufs + NIX_SQB_LIST_SPACE));
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txq->sqb_pool = rte_mempool_create_empty(name, NIX_MAX_SQB, blk_sz,
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0, 0, dev->node,
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MEMPOOL_F_NO_SPREAD);
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txq->nb_sqb_bufs = nb_sqb_bufs;
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txq->sqes_per_sqb_log2 = (uint16_t)rte_log2_u32(sqes_per_sqb);
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txq->nb_sqb_bufs_adj = nb_sqb_bufs -
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RTE_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb;
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txq->nb_sqb_bufs_adj =
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(NIX_SQB_LOWER_THRESH * txq->nb_sqb_bufs_adj) / 100;
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if (txq->sqb_pool == NULL) {
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otx2_err("Failed to allocate sqe mempool");
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goto fail;
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}
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memset(aura, 0, sizeof(*aura));
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aura->fc_ena = 1;
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aura->fc_addr = txq->fc_iova;
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aura->fc_hyst_bits = 0; /* Store count on all updates */
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if (rte_mempool_set_ops_byname(txq->sqb_pool, "octeontx2_npa", aura)) {
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otx2_err("Failed to set ops for sqe mempool");
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goto fail;
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}
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if (rte_mempool_populate_default(txq->sqb_pool) < 0) {
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otx2_err("Failed to populate sqe mempool");
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goto fail;
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}
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tmp = rte_mempool_calc_obj_size(blk_sz, MEMPOOL_F_NO_SPREAD, &sz);
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if (dev->sqb_size != sz.elt_size) {
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otx2_err("sqe pool block size is not expected %d != %d",
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dev->sqb_size, tmp);
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goto fail;
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}
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nix_sqb_aura_limit_cfg(txq->sqb_pool, txq->nb_sqb_bufs);
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return 0;
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fail:
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return -ENOMEM;
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}
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void
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otx2_nix_form_default_desc(struct otx2_eth_txq *txq)
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{
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struct nix_send_ext_s *send_hdr_ext;
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struct nix_send_hdr_s *send_hdr;
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struct nix_send_mem_s *send_mem;
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union nix_send_sg_s *sg;
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/* Initialize the fields based on basic single segment packet */
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memset(&txq->cmd, 0, sizeof(txq->cmd));
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if (txq->dev->tx_offload_flags & NIX_TX_NEED_EXT_HDR) {
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send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
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/* 2(HDR) + 2(EXT_HDR) + 1(SG) + 1(IOVA) = 6/2 - 1 = 2 */
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send_hdr->w0.sizem1 = 2;
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send_hdr_ext = (struct nix_send_ext_s *)&txq->cmd[2];
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send_hdr_ext->w0.subdc = NIX_SUBDC_EXT;
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if (txq->dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F) {
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/* Default: one seg packet would have:
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* 2(HDR) + 2(EXT) + 1(SG) + 1(IOVA) + 2(MEM)
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* => 8/2 - 1 = 3
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*/
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send_hdr->w0.sizem1 = 3;
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send_hdr_ext->w0.tstmp = 1;
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/* To calculate the offset for send_mem,
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* send_hdr->w0.sizem1 * 2
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*/
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send_mem = (struct nix_send_mem_s *)(txq->cmd +
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(send_hdr->w0.sizem1 << 1));
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send_mem->subdc = NIX_SUBDC_MEM;
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send_mem->dsz = 0x0;
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send_mem->wmem = 0x1;
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send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
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}
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sg = (union nix_send_sg_s *)&txq->cmd[4];
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} else {
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send_hdr = (struct nix_send_hdr_s *)&txq->cmd[0];
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/* 2(HDR) + 1(SG) + 1(IOVA) = 4/2 - 1 = 1 */
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send_hdr->w0.sizem1 = 1;
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sg = (union nix_send_sg_s *)&txq->cmd[2];
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}
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send_hdr->w0.sq = txq->sq;
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sg->subdc = NIX_SUBDC_SG;
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sg->segs = 1;
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sg->ld_type = NIX_SENDLDTYPE_LDD;
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rte_smp_wmb();
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}
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static void
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otx2_nix_tx_queue_release(void *_txq)
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{
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struct otx2_eth_txq *txq = _txq;
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if (!txq)
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return;
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otx2_nix_dbg("Releasing txq %u", txq->sq);
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/* Free sqb's and disable sq */
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nix_sq_uninit(txq);
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if (txq->sqb_pool) {
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rte_mempool_free(txq->sqb_pool);
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txq->sqb_pool = NULL;
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}
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rte_free(txq);
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}
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static int
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otx2_nix_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t sq,
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uint16_t nb_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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const struct rte_memzone *fc;
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struct otx2_eth_txq *txq;
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uint64_t offloads;
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int rc;
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rc = -EINVAL;
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/* Compile time check to make sure all fast path elements in a CL */
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RTE_BUILD_BUG_ON(offsetof(struct otx2_eth_txq, slow_path_start) >= 128);
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if (tx_conf->tx_deferred_start) {
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otx2_err("Tx deferred start is not supported");
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goto fail;
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}
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/* Free memory prior to re-allocation if needed. */
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if (eth_dev->data->tx_queues[sq] != NULL) {
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otx2_nix_dbg("Freeing memory prior to re-allocation %d", sq);
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otx2_nix_tx_queue_release(eth_dev->data->tx_queues[sq]);
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eth_dev->data->tx_queues[sq] = NULL;
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}
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/* Find the expected offloads for this queue */
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offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
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/* Allocating tx queue data structure */
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txq = rte_zmalloc_socket("otx2_ethdev TX queue", sizeof(*txq),
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OTX2_ALIGN, socket_id);
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if (txq == NULL) {
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otx2_err("Failed to alloc txq=%d", sq);
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rc = -ENOMEM;
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goto fail;
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}
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txq->sq = sq;
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txq->dev = dev;
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txq->sqb_pool = NULL;
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txq->offloads = offloads;
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dev->tx_offloads |= offloads;
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/*
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* Allocate memory for flow control updates from HW.
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* Alloc one cache line, so that fits all FC_STYPE modes.
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*/
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fc = rte_eth_dma_zone_reserve(eth_dev, "fcmem", sq,
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OTX2_ALIGN + sizeof(struct npa_aura_s),
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OTX2_ALIGN, dev->node);
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if (fc == NULL) {
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otx2_err("Failed to allocate mem for fcmem");
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rc = -ENOMEM;
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goto free_txq;
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}
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txq->fc_iova = fc->iova;
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txq->fc_mem = fc->addr;
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/* Initialize the aura sqb pool */
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rc = nix_alloc_sqb_pool(eth_dev->data->port_id, txq, nb_desc);
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if (rc) {
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otx2_err("Failed to alloc sqe pool rc=%d", rc);
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goto free_txq;
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}
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/* Initialize the SQ */
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rc = nix_sq_init(txq);
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if (rc) {
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otx2_err("Failed to init sq=%d context", sq);
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goto free_txq;
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}
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txq->fc_cache_pkts = 0;
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txq->io_addr = dev->base + NIX_LF_OP_SENDX(0);
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/* Evenly distribute LMT slot for each sq */
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txq->lmt_addr = (void *)(dev->lmt_addr + ((sq & LMT_SLOT_MASK) << 12));
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txq->qconf.socket_id = socket_id;
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txq->qconf.nb_desc = nb_desc;
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memcpy(&txq->qconf.conf.tx, tx_conf, sizeof(struct rte_eth_txconf));
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otx2_nix_form_default_desc(txq);
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otx2_nix_dbg("sq=%d fc=%p offload=0x%" PRIx64 " sqb=0x%" PRIx64 ""
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" lmt_addr=%p nb_sqb_bufs=%d sqes_per_sqb_log2=%d", sq,
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fc->addr, offloads, txq->sqb_pool->pool_id, txq->lmt_addr,
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txq->nb_sqb_bufs, txq->sqes_per_sqb_log2);
|
||||
eth_dev->data->tx_queues[sq] = txq;
|
||||
eth_dev->data->tx_queue_state[sq] = RTE_ETH_QUEUE_STATE_STOPPED;
|
||||
return 0;
|
||||
|
||||
free_txq:
|
||||
otx2_nix_tx_queue_release(txq);
|
||||
fail:
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
otx2_nix_configure(struct rte_eth_dev *eth_dev)
|
||||
{
|
||||
@ -549,6 +935,8 @@ static const struct eth_dev_ops otx2_eth_dev_ops = {
|
||||
.dev_infos_get = otx2_nix_info_get,
|
||||
.dev_configure = otx2_nix_configure,
|
||||
.link_update = otx2_nix_link_update,
|
||||
.tx_queue_setup = otx2_nix_tx_queue_setup,
|
||||
.tx_queue_release = otx2_nix_tx_queue_release,
|
||||
.rx_queue_setup = otx2_nix_rx_queue_setup,
|
||||
.rx_queue_release = otx2_nix_rx_queue_release,
|
||||
.stats_get = otx2_nix_dev_stats_get,
|
||||
@ -763,12 +1151,26 @@ otx2_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool mbox_close)
|
||||
{
|
||||
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
|
||||
struct rte_pci_device *pci_dev;
|
||||
int rc;
|
||||
int rc, i;
|
||||
|
||||
/* Nothing to be done for secondary processes */
|
||||
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
|
||||
return 0;
|
||||
|
||||
/* Free up SQs */
|
||||
for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
|
||||
otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
|
||||
eth_dev->data->tx_queues[i] = NULL;
|
||||
}
|
||||
eth_dev->data->nb_tx_queues = 0;
|
||||
|
||||
/* Free up RQ's and CQ's */
|
||||
for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
|
||||
otx2_nix_rx_queue_release(eth_dev->data->rx_queues[i]);
|
||||
eth_dev->data->rx_queues[i] = NULL;
|
||||
}
|
||||
eth_dev->data->nb_rx_queues = 0;
|
||||
|
||||
/* Unregister queue irqs */
|
||||
oxt2_nix_unregister_queue_irqs(eth_dev);
|
||||
|
||||
|
||||
@ -19,6 +19,7 @@
|
||||
#include "otx2_irq.h"
|
||||
#include "otx2_mempool.h"
|
||||
#include "otx2_rx.h"
|
||||
#include "otx2_tx.h"
|
||||
|
||||
#define OTX2_ETH_DEV_PMD_VERSION "1.0"
|
||||
|
||||
@ -62,6 +63,7 @@
|
||||
|
||||
#define NIX_MAX_SQB 512
|
||||
#define NIX_MIN_SQB 32
|
||||
#define NIX_SQB_LIST_SPACE 2
|
||||
#define NIX_RSS_RETA_SIZE_MAX 256
|
||||
/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
|
||||
#define NIX_RSS_GRPS 8
|
||||
@ -72,6 +74,8 @@
|
||||
#define NIX_RX_NB_SEG_MAX 6
|
||||
#define NIX_CQ_ENTRY_SZ 128
|
||||
#define NIX_CQ_ALIGN 512
|
||||
#define NIX_SQB_LOWER_THRESH 90
|
||||
#define LMT_SLOT_MASK 0x7f
|
||||
|
||||
/* If PTP is enabled additional SEND MEM DESC is required which
|
||||
* takes 2 words, hence max 7 iova address are possible
|
||||
@ -204,6 +208,24 @@ struct otx2_eth_dev {
|
||||
struct rte_eth_dev *eth_dev;
|
||||
} __rte_cache_aligned;
|
||||
|
||||
struct otx2_eth_txq {
|
||||
uint64_t cmd[8];
|
||||
int64_t fc_cache_pkts;
|
||||
uint64_t *fc_mem;
|
||||
void *lmt_addr;
|
||||
rte_iova_t io_addr;
|
||||
rte_iova_t fc_iova;
|
||||
uint16_t sqes_per_sqb_log2;
|
||||
int16_t nb_sqb_bufs_adj;
|
||||
MARKER slow_path_start;
|
||||
uint16_t nb_sqb_bufs;
|
||||
uint16_t sq;
|
||||
uint64_t offloads;
|
||||
struct otx2_eth_dev *dev;
|
||||
struct rte_mempool *sqb_pool;
|
||||
struct otx2_eth_qconf qconf;
|
||||
} __rte_cache_aligned;
|
||||
|
||||
struct otx2_eth_rxq {
|
||||
uint64_t mbuf_initializer;
|
||||
uint64_t data_off;
|
||||
@ -329,4 +351,7 @@ int otx2_cgx_mac_max_entries_get(struct otx2_eth_dev *dev);
|
||||
int otx2_ethdev_parse_devargs(struct rte_devargs *devargs,
|
||||
struct otx2_eth_dev *dev);
|
||||
|
||||
/* Rx and Tx routines */
|
||||
void otx2_nix_form_default_desc(struct otx2_eth_txq *txq);
|
||||
|
||||
#endif /* __OTX2_ETHDEV_H__ */
|
||||
|
||||
@ -144,5 +144,6 @@ otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo)
|
||||
ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
|
||||
ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G;
|
||||
|
||||
devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP;
|
||||
devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
|
||||
RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
|
||||
}
|
||||
|
||||
28
drivers/net/octeontx2/otx2_tx.h
Normal file
28
drivers/net/octeontx2/otx2_tx.h
Normal file
@ -0,0 +1,28 @@
|
||||
/* SPDX-License-Identifier: BSD-3-Clause
|
||||
* Copyright(C) 2019 Marvell International Ltd.
|
||||
*/
|
||||
|
||||
#ifndef __OTX2_TX_H__
|
||||
#define __OTX2_TX_H__
|
||||
|
||||
#define NIX_TX_OFFLOAD_NONE (0)
|
||||
#define NIX_TX_OFFLOAD_L3_L4_CSUM_F BIT(0)
|
||||
#define NIX_TX_OFFLOAD_OL3_OL4_CSUM_F BIT(1)
|
||||
#define NIX_TX_OFFLOAD_VLAN_QINQ_F BIT(2)
|
||||
#define NIX_TX_OFFLOAD_MBUF_NOFF_F BIT(3)
|
||||
#define NIX_TX_OFFLOAD_TSTAMP_F BIT(4)
|
||||
|
||||
/* Flags to control xmit_prepare function.
|
||||
* Defining it from backwards to denote its been
|
||||
* not used as offload flags to pick function
|
||||
*/
|
||||
#define NIX_TX_MULTI_SEG_F BIT(15)
|
||||
|
||||
#define NIX_TX_NEED_SEND_HDR_W1 \
|
||||
(NIX_TX_OFFLOAD_L3_L4_CSUM_F | NIX_TX_OFFLOAD_OL3_OL4_CSUM_F | \
|
||||
NIX_TX_OFFLOAD_VLAN_QINQ_F)
|
||||
|
||||
#define NIX_TX_NEED_EXT_HDR \
|
||||
(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F)
|
||||
|
||||
#endif /* __OTX2_TX_H__ */
|
||||
Loading…
x
Reference in New Issue
Block a user