ixgbe: support ieee1588 functions for device time
Add additional functions to support the existing IEEE1588 functionality and to enable getting, setting and adjusting the device time. Signed-off-by: Daniel Mrzyglod <danielx.t.mrzyglod@intel.com> Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com> Reviewed-by: John McNamara <john.mcnamara@intel.com>
This commit is contained in:
Daniel Mrzyglod
Thomas Monjalon
parent
b6fd85cd65
commit
1c4445e1f2
@ -126,10 +126,17 @@
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#define IXGBE_HKEY_MAX_INDEX 10
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/* Additional timesync values. */
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#define IXGBE_TIMINCA_16NS_SHIFT 24
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#define IXGBE_TIMINCA_INCVALUE 16000000
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#define IXGBE_TIMINCA_INIT ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
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| IXGBE_TIMINCA_INCVALUE)
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#define NSEC_PER_SEC 1000000000L
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#define IXGBE_INCVAL_10GB 0x66666666
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#define IXGBE_INCVAL_1GB 0x40000000
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#define IXGBE_INCVAL_100 0x50000000
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#define IXGBE_INCVAL_SHIFT_10GB 28
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#define IXGBE_INCVAL_SHIFT_1GB 24
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#define IXGBE_INCVAL_SHIFT_100 21
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#define IXGBE_INCVAL_SHIFT_82599 7
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#define IXGBE_INCPER_SHIFT_82599 24
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#define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffff
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static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
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static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
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@ -325,6 +332,11 @@ static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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uint32_t flags);
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static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
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static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
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struct timespec *timestamp);
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static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
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const struct timespec *timestamp);
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/*
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* Define VF Stats MACRO for Non "cleared on read" register
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@ -480,6 +492,9 @@ static const struct eth_dev_ops ixgbe_eth_dev_ops = {
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.get_eeprom = ixgbe_get_eeprom,
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.set_eeprom = ixgbe_set_eeprom,
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.get_dcb_info = ixgbe_dev_get_dcb_info,
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.timesync_adjust_time = ixgbe_timesync_adjust_time,
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.timesync_read_time = ixgbe_timesync_read_time,
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.timesync_write_time = ixgbe_timesync_write_time,
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};
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/*
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@ -5582,6 +5597,186 @@ ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
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ixgbe_dev_addr_list_itr, TRUE);
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}
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static uint64_t
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ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t systime_cycles;
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switch (hw->mac.type) {
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case ixgbe_mac_X550:
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/* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
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systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
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systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
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* NSEC_PER_SEC;
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break;
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default:
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systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
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systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
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<< 32;
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}
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return systime_cycles;
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}
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static uint64_t
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ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t rx_tstamp_cycles;
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switch (hw->mac.type) {
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case ixgbe_mac_X550:
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/* RXSTMPL stores ns and RXSTMPH stores seconds. */
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rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
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rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
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* NSEC_PER_SEC;
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break;
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default:
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/* RXSTMPL stores ns and RXSTMPH stores seconds. */
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rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
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rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
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<< 32;
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}
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return rx_tstamp_cycles;
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}
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static uint64_t
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ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint64_t tx_tstamp_cycles;
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switch (hw->mac.type) {
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case ixgbe_mac_X550:
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/* TXSTMPL stores ns and TXSTMPH stores seconds. */
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tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
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tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
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* NSEC_PER_SEC;
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break;
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default:
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/* TXSTMPL stores ns and TXSTMPH stores seconds. */
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tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
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tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
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<< 32;
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}
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return tx_tstamp_cycles;
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}
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static void
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ixgbe_start_timecounters(struct rte_eth_dev *dev)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct ixgbe_adapter *adapter =
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(struct ixgbe_adapter *)dev->data->dev_private;
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struct rte_eth_link link;
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uint32_t incval = 0;
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uint32_t shift = 0;
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/* Get current link speed. */
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memset(&link, 0, sizeof(link));
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ixgbe_dev_link_update(dev, 1);
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rte_ixgbe_dev_atomic_read_link_status(dev, &link);
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switch (link.link_speed) {
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case ETH_LINK_SPEED_100:
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incval = IXGBE_INCVAL_100;
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shift = IXGBE_INCVAL_SHIFT_100;
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break;
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case ETH_LINK_SPEED_1000:
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incval = IXGBE_INCVAL_1GB;
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shift = IXGBE_INCVAL_SHIFT_1GB;
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break;
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case ETH_LINK_SPEED_10000:
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default:
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incval = IXGBE_INCVAL_10GB;
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shift = IXGBE_INCVAL_SHIFT_10GB;
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break;
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}
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switch (hw->mac.type) {
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case ixgbe_mac_X550:
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/* Independent of link speed. */
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incval = 1;
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/* Cycles read will be interpreted as ns. */
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shift = 0;
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/* Fall-through */
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case ixgbe_mac_X540:
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IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
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break;
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case ixgbe_mac_82599EB:
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incval >>= IXGBE_INCVAL_SHIFT_82599;
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shift -= IXGBE_INCVAL_SHIFT_82599;
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IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
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(1 << IXGBE_INCPER_SHIFT_82599) | incval);
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break;
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default:
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/* Not supported. */
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return;
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}
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memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
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memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
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adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
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adapter->systime_tc.cc_shift = shift;
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adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
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adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
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adapter->rx_tstamp_tc.cc_shift = shift;
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adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
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adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
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adapter->tx_tstamp_tc.cc_shift = shift;
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adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
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}
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static int
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ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
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{
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struct ixgbe_adapter *adapter =
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(struct ixgbe_adapter *)dev->data->dev_private;
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adapter->systime_tc.nsec += delta;
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adapter->rx_tstamp_tc.nsec += delta;
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adapter->tx_tstamp_tc.nsec += delta;
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return 0;
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}
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static int
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ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
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{
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uint64_t ns;
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struct ixgbe_adapter *adapter =
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(struct ixgbe_adapter *)dev->data->dev_private;
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ns = rte_timespec_to_ns(ts);
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/* Set the timecounters to a new value. */
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adapter->systime_tc.nsec = ns;
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adapter->rx_tstamp_tc.nsec = ns;
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adapter->tx_tstamp_tc.nsec = ns;
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return 0;
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}
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static int
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ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
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{
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uint64_t ns, systime_cycles;
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struct ixgbe_adapter *adapter =
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(struct ixgbe_adapter *)dev->data->dev_private;
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systime_cycles = ixgbe_read_systime_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
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*ts = rte_ns_to_timespec(ns);
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return 0;
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}
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static int
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ixgbe_timesync_enable(struct rte_eth_dev *dev)
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{
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@ -5589,13 +5784,18 @@ ixgbe_timesync_enable(struct rte_eth_dev *dev)
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uint32_t tsync_ctl;
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uint32_t tsauxc;
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/* Stop the timesync system time. */
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IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
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/* Reset the timesync system time value. */
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IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
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IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
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/* Enable system time for platforms where it isn't on by default. */
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tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
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tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
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IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
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/* Start incrementing the register used to timestamp PTP packets. */
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IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
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ixgbe_start_timecounters(dev);
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/* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
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IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
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@ -5613,6 +5813,8 @@ ixgbe_timesync_enable(struct rte_eth_dev *dev)
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tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
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IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
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IXGBE_WRITE_FLUSH(hw);
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return 0;
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}
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@ -5647,19 +5849,19 @@ ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
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uint32_t flags __rte_unused)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct ixgbe_adapter *adapter =
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(struct ixgbe_adapter *)dev->data->dev_private;
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uint32_t tsync_rxctl;
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uint32_t rx_stmpl;
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uint32_t rx_stmph;
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uint64_t rx_tstamp_cycles;
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uint64_t ns;
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tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
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if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
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return -EINVAL;
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rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
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rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
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timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
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timestamp->tv_nsec = 0;
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rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
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*timestamp = rte_ns_to_timespec(ns);
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return 0;
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}
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@ -5669,21 +5871,21 @@ ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
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struct timespec *timestamp)
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{
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struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct ixgbe_adapter *adapter =
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(struct ixgbe_adapter *)dev->data->dev_private;
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uint32_t tsync_txctl;
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uint32_t tx_stmpl;
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uint32_t tx_stmph;
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uint64_t tx_tstamp_cycles;
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uint64_t ns;
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tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
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if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
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return -EINVAL;
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tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
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tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
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tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
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ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
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*timestamp = rte_ns_to_timespec(ns);
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timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
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timestamp->tv_nsec = 0;
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return 0;
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return 0;
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}
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static int
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@ -37,6 +37,7 @@
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#include "base/ixgbe_dcb_82599.h"
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#include "base/ixgbe_dcb_82598.h"
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#include "ixgbe_bypass.h"
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#include <rte_time.h>
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/* need update link, bit flag */
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#define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
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@ -282,6 +283,9 @@ struct ixgbe_adapter {
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bool rx_bulk_alloc_allowed;
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bool rx_vec_allowed;
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struct rte_timecounter systime_tc;
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struct rte_timecounter rx_tstamp_tc;
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struct rte_timecounter tx_tstamp_tc;
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};
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#define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
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