mempool/octeontx: probe fpavf PCIe devices
A mempool device is set of PCIe vfs. On Octeontx HW, each mempool devices are enumerated as separate SRIOV VF PCIe device. In order to expose as a mempool device: On PCIe probe, the driver stores the information associated with the PCIe device and later upon application pool request (e.g. rte_mempool_create_empty), Infrastructure creates a pool device with earlier probed PCIe VF devices. Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This commit is contained in:
Santosh Shukla
Thomas Monjalon
parent
8700239f77
commit
1c842786fe
@ -29,3 +29,154 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <errno.h>
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#include <sys/mman.h>
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#include <rte_atomic.h>
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#include <rte_eal.h>
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#include <rte_pci.h>
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#include <rte_errno.h>
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#include <rte_memory.h>
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#include <rte_malloc.h>
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#include <rte_spinlock.h>
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#include "octeontx_fpavf.h"
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struct fpavf_res {
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void *pool_stack_base;
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void *bar0;
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uint64_t stack_ln_ptr;
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uint16_t domain_id;
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uint16_t vf_id; /* gpool_id */
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uint16_t sz128; /* Block size in cache lines */
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bool is_inuse;
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};
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struct octeontx_fpadev {
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rte_spinlock_t lock;
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uint8_t total_gpool_cnt;
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struct fpavf_res pool[FPA_VF_MAX];
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};
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static struct octeontx_fpadev fpadev;
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static void
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octeontx_fpavf_setup(void)
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{
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uint8_t i;
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static bool init_once;
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if (!init_once) {
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rte_spinlock_init(&fpadev.lock);
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fpadev.total_gpool_cnt = 0;
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for (i = 0; i < FPA_VF_MAX; i++) {
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fpadev.pool[i].domain_id = ~0;
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fpadev.pool[i].stack_ln_ptr = 0;
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fpadev.pool[i].sz128 = 0;
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fpadev.pool[i].bar0 = NULL;
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fpadev.pool[i].pool_stack_base = NULL;
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fpadev.pool[i].is_inuse = false;
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}
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init_once = 1;
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}
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}
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static int
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octeontx_fpavf_identify(void *bar0)
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{
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uint64_t val;
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uint16_t domain_id;
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uint16_t vf_id;
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uint64_t stack_ln_ptr;
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val = fpavf_read64((void *)((uintptr_t)bar0 +
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FPA_VF_VHAURA_CNT_THRESHOLD(0)));
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domain_id = (val >> 8) & 0xffff;
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vf_id = (val >> 24) & 0xffff;
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stack_ln_ptr = fpavf_read64((void *)((uintptr_t)bar0 +
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FPA_VF_VHPOOL_THRESHOLD(0)));
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if (vf_id >= FPA_VF_MAX) {
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fpavf_log_err("vf_id(%d) greater than max vf (32)\n", vf_id);
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return -1;
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}
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if (fpadev.pool[vf_id].is_inuse) {
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fpavf_log_err("vf_id %d is_inuse\n", vf_id);
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return -1;
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}
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fpadev.pool[vf_id].domain_id = domain_id;
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fpadev.pool[vf_id].vf_id = vf_id;
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fpadev.pool[vf_id].bar0 = bar0;
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fpadev.pool[vf_id].stack_ln_ptr = stack_ln_ptr;
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/* SUCCESS */
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return vf_id;
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}
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/* FPAVF pcie device aka mempool probe */
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static int
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fpavf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
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{
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uint8_t *idreg;
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int res;
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struct fpavf_res *fpa;
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RTE_SET_USED(pci_drv);
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RTE_SET_USED(fpa);
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/* For secondary processes, the primary has done all the work */
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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return 0;
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if (pci_dev->mem_resource[0].addr == NULL) {
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fpavf_log_err("Empty bars %p ", pci_dev->mem_resource[0].addr);
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return -ENODEV;
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}
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idreg = pci_dev->mem_resource[0].addr;
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octeontx_fpavf_setup();
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res = octeontx_fpavf_identify(idreg);
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if (res < 0)
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return -1;
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fpa = &fpadev.pool[res];
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fpadev.total_gpool_cnt++;
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rte_wmb();
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fpavf_log_dbg("total_fpavfs %d bar0 %p domain %d vf %d stk_ln_ptr 0x%x",
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fpadev.total_gpool_cnt, fpa->bar0, fpa->domain_id,
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fpa->vf_id, (unsigned int)fpa->stack_ln_ptr);
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return 0;
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}
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static const struct rte_pci_id pci_fpavf_map[] = {
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{
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RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
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PCI_DEVICE_ID_OCTEONTX_FPA_VF)
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},
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{
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.vendor_id = 0,
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},
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};
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static struct rte_pci_driver pci_fpavf = {
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.id_table = pci_fpavf_map,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
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.probe = fpavf_probe,
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};
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RTE_PMD_REGISTER_PCI(octeontx_fpavf, pci_fpavf);
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@ -34,6 +34,7 @@
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#define __OCTEONTX_FPAVF_H__
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#include <rte_debug.h>
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#include <rte_io.h>
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#ifdef RTE_LIBRTE_OCTEONTX_MEMPOOL_DEBUG
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#define fpavf_log_info(fmt, args...) \
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@ -87,4 +88,42 @@
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#define FPA_VF0_APERTURE_SHIFT 22
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#define FPA_AURA_SET_SIZE 16
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/*
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* In Cavium OcteonTX SoC, all accesses to the device registers are
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* implicitly strongly ordered. So, the relaxed version of IO operation is
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* safe to use with out any IO memory barriers.
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*/
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#define fpavf_read64 rte_read64_relaxed
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#define fpavf_write64 rte_write64_relaxed
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/* ARM64 specific functions */
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#if defined(RTE_ARCH_ARM64)
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#define fpavf_load_pair(val0, val1, addr) ({ \
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asm volatile( \
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"ldp %x[x0], %x[x1], [%x[p1]]" \
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:[x0]"=r"(val0), [x1]"=r"(val1) \
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:[p1]"r"(addr) \
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); })
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#define fpavf_store_pair(val0, val1, addr) ({ \
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asm volatile( \
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"stp %x[x0], %x[x1], [%x[p1]]" \
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::[x0]"r"(val0), [x1]"r"(val1), [p1]"r"(addr) \
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); })
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#else /* Un optimized functions for building on non arm64 arch */
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#define fpavf_load_pair(val0, val1, addr) \
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do { \
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val0 = rte_read64(addr); \
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val1 = rte_read64(((uint8_t *)addr) + 8); \
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} while (0)
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#define fpavf_store_pair(val0, val1, addr) \
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do { \
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rte_write64(val0, addr); \
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rte_write64(val1, (((uint8_t *)addr) + 8)); \
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} while (0)
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#endif
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#endif /* __OCTEONTX_FPAVF_H__ */
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