net/bnxt: add device configure operation
The dev_configure_op function calls bnxt_set_hwrm_link_config() to setup the PHY. This calls the new bnxt_parse_eth_link_*() functions to translate from the DPDK macro values to those used by HWRM calls, then calls bnxt_hwrm_port_phy_cfg() to issue the HWRM call. New HWRM calls: bnxt_hwrm_port_phy_cfg: This command configures the PHY device for the port. Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com> Signed-off-by: Stephen Hurd <stephen.hurd@broadcom.com> Reviewed-by: David Christensen <david.christensen@broadcom.com>
This commit is contained in:
Ajit Khaparde
Bruce Richardson
parent
0a6d2a7200
commit
1d0704f4d7
@ -81,6 +81,29 @@ struct bnxt_pf_info {
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struct bnxt_vf_info *vf;
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};
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/* Max wait time is 10 * 100ms = 1s */
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#define BNXT_LINK_WAIT_CNT 10
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#define BNXT_LINK_WAIT_INTERVAL 100
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struct bnxt_link_info {
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uint8_t phy_flags;
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uint8_t mac_type;
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uint8_t phy_link_status;
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uint8_t loop_back;
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uint8_t link_up;
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uint8_t duplex;
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uint8_t pause;
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uint8_t force_pause;
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uint8_t auto_pause;
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uint8_t auto_mode;
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#define PHY_VER_LEN 3
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uint8_t phy_ver[PHY_VER_LEN];
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uint16_t link_speed;
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uint16_t support_speeds;
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uint16_t auto_link_speed;
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uint16_t auto_link_speed_mask;
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uint32_t preemphasis;
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};
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#define BNXT_COS_QUEUE_COUNT 8
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struct bnxt_cos_queue_info {
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uint8_t id;
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@ -99,6 +122,14 @@ struct bnxt {
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#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
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#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
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unsigned int rx_nr_rings;
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unsigned int rx_cp_nr_rings;
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struct bnxt_rx_queue **rx_queues;
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unsigned int tx_nr_rings;
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unsigned int tx_cp_nr_rings;
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struct bnxt_tx_queue **tx_queues;
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#define MAX_NUM_MAC_ADDR 32
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uint8_t mac_addr[ETHER_ADDR_LEN];
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@ -109,6 +140,7 @@ struct bnxt {
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uint16_t max_req_len;
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uint16_t max_resp_len;
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struct bnxt_link_info link_info;
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struct bnxt_cos_queue_info cos_queue[BNXT_COS_QUEUE_COUNT];
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struct bnxt_pf_info pf;
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@ -154,6 +154,29 @@ static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
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dev_info->vmdq_queue_base = 0;
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}
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/* Configure the device based on the configuration provided */
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static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev)
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{
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struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
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int rc;
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bp->rx_queues = (void *)eth_dev->data->rx_queues;
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bp->tx_queues = (void *)eth_dev->data->tx_queues;
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/* Inherit new configurations */
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bp->rx_nr_rings = eth_dev->data->nb_rx_queues;
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bp->tx_nr_rings = eth_dev->data->nb_tx_queues;
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bp->rx_cp_nr_rings = bp->rx_nr_rings;
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bp->tx_cp_nr_rings = bp->tx_nr_rings;
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if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
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eth_dev->data->mtu =
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eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
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ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
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rc = bnxt_set_hwrm_link_config(bp, true);
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return rc;
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}
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/*
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* Initialization
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*/
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@ -161,6 +184,7 @@ static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
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static struct eth_dev_ops bnxt_dev_ops = {
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.dev_infos_get = bnxt_dev_info_get_op,
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.dev_close = bnxt_dev_close_op,
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.dev_configure = bnxt_dev_configure_op,
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};
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static bool bnxt_vf_pciid(uint16_t id)
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@ -314,6 +314,61 @@ int bnxt_hwrm_func_driver_unregister(struct bnxt *bp, uint32_t flags)
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return rc;
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}
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static int bnxt_hwrm_port_phy_cfg(struct bnxt *bp, struct bnxt_link_info *conf)
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{
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int rc = 0;
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struct hwrm_port_phy_cfg_input req = {.req_type = 0};
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struct hwrm_port_phy_cfg_output *resp = bp->hwrm_cmd_resp_addr;
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HWRM_PREP(req, PORT_PHY_CFG, -1, resp);
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req.flags = conf->phy_flags;
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if (conf->link_up) {
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req.force_link_speed = conf->link_speed;
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/*
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* Note, ChiMP FW 20.2.1 and 20.2.2 return an error when we set
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* any auto mode, even "none".
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*/
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if (req.auto_mode == HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE) {
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req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE;
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} else {
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req.auto_mode = conf->auto_mode;
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req.enables |=
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HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE;
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req.auto_link_speed_mask = conf->auto_link_speed_mask;
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req.enables |=
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HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK;
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req.auto_link_speed = conf->auto_link_speed;
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req.enables |=
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HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED;
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}
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req.auto_duplex = conf->duplex;
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req.enables |= HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX;
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req.auto_pause = conf->auto_pause;
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/* Set force_pause if there is no auto or if there is a force */
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if (req.auto_pause)
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req.enables |=
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HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE;
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else
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req.enables |=
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HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
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req.force_pause = conf->force_pause;
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if (req.force_pause)
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req.enables |=
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HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE;
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} else {
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req.flags &= ~HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
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req.flags |= HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN;
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req.force_link_speed = 0;
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}
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rc = bnxt_hwrm_send_message(bp, &req, sizeof(req));
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HWRM_CHECK_RESULT;
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return rc;
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}
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int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
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{
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int rc = 0;
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@ -372,3 +427,178 @@ int bnxt_alloc_hwrm_resources(struct bnxt *bp)
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return 0;
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}
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static uint16_t bnxt_parse_eth_link_duplex(uint32_t conf_link_speed)
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{
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uint8_t hw_link_duplex = HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
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if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
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return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH;
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switch (conf_link_speed) {
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case ETH_LINK_SPEED_10M_HD:
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case ETH_LINK_SPEED_100M_HD:
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return HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF;
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}
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return hw_link_duplex;
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}
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static uint16_t bnxt_parse_eth_link_speed(uint32_t conf_link_speed)
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{
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uint16_t eth_link_speed = 0;
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if ((conf_link_speed & ETH_LINK_SPEED_FIXED) == ETH_LINK_SPEED_AUTONEG)
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return ETH_LINK_SPEED_AUTONEG;
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switch (conf_link_speed & ~ETH_LINK_SPEED_FIXED) {
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case ETH_LINK_SPEED_100M:
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case ETH_LINK_SPEED_100M_HD:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB;
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break;
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case ETH_LINK_SPEED_1G:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
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break;
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case ETH_LINK_SPEED_2_5G:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
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break;
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case ETH_LINK_SPEED_10G:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
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break;
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case ETH_LINK_SPEED_20G:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
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break;
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case ETH_LINK_SPEED_25G:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
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break;
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case ETH_LINK_SPEED_40G:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
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break;
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case ETH_LINK_SPEED_50G:
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eth_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
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break;
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default:
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RTE_LOG(ERR, PMD,
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"Unsupported link speed %d; default to AUTO\n",
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conf_link_speed);
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break;
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}
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return eth_link_speed;
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}
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#define BNXT_SUPPORTED_SPEEDS (ETH_LINK_SPEED_100M | ETH_LINK_SPEED_100M_HD | \
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ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G | \
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ETH_LINK_SPEED_10G | ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G | \
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ETH_LINK_SPEED_40G | ETH_LINK_SPEED_50G)
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static int bnxt_valid_link_speed(uint32_t link_speed, uint8_t port_id)
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{
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uint32_t one_speed;
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if (link_speed == ETH_LINK_SPEED_AUTONEG)
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return 0;
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if (link_speed & ETH_LINK_SPEED_FIXED) {
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one_speed = link_speed & ~ETH_LINK_SPEED_FIXED;
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if (one_speed & (one_speed - 1)) {
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RTE_LOG(ERR, PMD,
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"Invalid advertised speeds (%u) for port %u\n",
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link_speed, port_id);
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return -EINVAL;
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}
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if ((one_speed & BNXT_SUPPORTED_SPEEDS) != one_speed) {
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RTE_LOG(ERR, PMD,
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"Unsupported advertised speed (%u) for port %u\n",
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link_speed, port_id);
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return -EINVAL;
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}
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} else {
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if (!(link_speed & BNXT_SUPPORTED_SPEEDS)) {
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RTE_LOG(ERR, PMD,
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"Unsupported advertised speeds (%u) for port %u\n",
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link_speed, port_id);
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return -EINVAL;
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}
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}
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return 0;
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}
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static uint16_t bnxt_parse_eth_link_speed_mask(uint32_t link_speed)
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{
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uint16_t ret = 0;
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if (link_speed == ETH_LINK_SPEED_AUTONEG)
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link_speed = BNXT_SUPPORTED_SPEEDS;
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if (link_speed & ETH_LINK_SPEED_100M)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
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if (link_speed & ETH_LINK_SPEED_100M_HD)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB;
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if (link_speed & ETH_LINK_SPEED_1G)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB;
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if (link_speed & ETH_LINK_SPEED_2_5G)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB;
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if (link_speed & ETH_LINK_SPEED_10G)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB;
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if (link_speed & ETH_LINK_SPEED_20G)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB;
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if (link_speed & ETH_LINK_SPEED_25G)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB;
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if (link_speed & ETH_LINK_SPEED_40G)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB;
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if (link_speed & ETH_LINK_SPEED_50G)
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ret |= HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB;
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return ret;
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}
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int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up)
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{
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int rc = 0;
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struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
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struct bnxt_link_info link_req;
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uint16_t speed;
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rc = bnxt_valid_link_speed(dev_conf->link_speeds,
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bp->eth_dev->data->port_id);
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if (rc)
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goto error;
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memset(&link_req, 0, sizeof(link_req));
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speed = bnxt_parse_eth_link_speed(dev_conf->link_speeds);
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link_req.link_up = link_up;
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if (speed == 0) {
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link_req.phy_flags =
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HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG;
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link_req.auto_mode =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW;
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link_req.auto_link_speed_mask =
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bnxt_parse_eth_link_speed_mask(dev_conf->link_speeds);
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link_req.auto_link_speed =
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HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB;
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} else {
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link_req.auto_mode = HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE;
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link_req.phy_flags = HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE |
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HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY;
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link_req.link_speed = speed;
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}
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link_req.duplex = bnxt_parse_eth_link_duplex(dev_conf->link_speeds);
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link_req.auto_pause = bp->link_info.auto_pause;
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link_req.force_pause = bp->link_info.force_pause;
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rc = bnxt_hwrm_port_phy_cfg(bp, &link_req);
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if (rc) {
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RTE_LOG(ERR, PMD,
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"Set link config failed with rc %d\n", rc);
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}
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error:
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return rc;
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}
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@ -52,5 +52,6 @@ int bnxt_hwrm_ver_get(struct bnxt *bp);
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void bnxt_free_hwrm_resources(struct bnxt *bp);
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int bnxt_alloc_hwrm_resources(struct bnxt *bp);
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int bnxt_set_hwrm_link_config(struct bnxt *bp, bool link_up);
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#endif
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@ -54,6 +54,7 @@
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#define HWRM_FUNC_QCAPS (UINT32_C(0x15))
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#define HWRM_FUNC_DRV_UNRGTR (UINT32_C(0x1a))
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#define HWRM_FUNC_DRV_RGTR (UINT32_C(0x1d))
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#define HWRM_PORT_PHY_CFG (UINT32_C(0x20))
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#define HWRM_QUEUE_QPORTCFG (UINT32_C(0x30))
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/*
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@ -345,6 +346,475 @@ struct hwrm_func_qcaps_output {
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uint8_t valid;
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} __attribute__((packed));
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/* hwrm_port_phy_cfg */
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/*
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* Description: This command configures the PHY device for the port. It allows
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* setting of the most generic settings for the PHY. The HWRM shall complete
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* this command as soon as PHY settings are configured. They may not be applied
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* when the command response is provided. A VF driver shall not be allowed to
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* configure PHY using this command. In a network partition mode, a PF driver
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* shall not be allowed to configure PHY using this command.
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*/
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/* Input (56 bytes) */
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struct hwrm_port_phy_cfg_input {
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/*
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* This value indicates what type of request this is. The format for the
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* rest of the command is determined by this field.
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*/
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uint16_t req_type;
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/*
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* This value indicates the what completion ring the request will be
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* optionally completed on. If the value is -1, then no CR completion
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* will be generated. Any other value must be a valid CR ring_id value
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* for this function.
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*/
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uint16_t cmpl_ring;
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/* This value indicates the command sequence number. */
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uint16_t seq_id;
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/*
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* Target ID of this command. 0x0 - 0xFFF8 - Used for function ids
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* 0xFFF8 - 0xFFFE - Reserved for internal processors 0xFFFF - HWRM
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*/
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uint16_t target_id;
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/*
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* This is the host address where the response will be written when the
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* request is complete. This area must be 16B aligned and must be
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* cleared to zero before the request is made.
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*/
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uint64_t resp_addr;
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/*
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* When this bit is set to '1', the PHY for the port shall be reset. #
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* If this bit is set to 1, then the HWRM shall reset the PHY after
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* applying PHY configuration changes specified in this command. # In
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* order to guarantee that PHY configuration changes specified in this
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* command take effect, the HWRM client should set this flag to 1. # If
|
||||
* this bit is not set to 1, then the HWRM may reset the PHY depending
|
||||
* on the current PHY configuration and settings specified in this
|
||||
* command.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESET_PHY UINT32_C(0x1)
|
||||
/*
|
||||
* When this bit is set to '1', the link shall be forced to be taken
|
||||
* down. # When this bit is set to '1", all other command input settings
|
||||
* related to the link speed shall be ignored. Once the link state is
|
||||
* forced down, it can be explicitly cleared from that state by setting
|
||||
* this flag to '0'. # If this flag is set to '0', then the link shall
|
||||
* be cleared from forced down state if the link is in forced down
|
||||
* state. There may be conditions (e.g. out-of-band or sideband
|
||||
* configuration changes for the link) outside the scope of the HWRM
|
||||
* implementation that may clear forced down link state.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE_LINK_DOWN UINT32_C(0x2)
|
||||
/*
|
||||
* When this bit is set to '1', the link shall be forced to the
|
||||
* force_link_speed value. When this bit is set to '1', the HWRM client
|
||||
* should not enable any of the auto negotiation related fields
|
||||
* represented by auto_XXX fields in this command. When this bit is set
|
||||
* to '1' and the HWRM client has enabled a auto_XXX field in this
|
||||
* command, then the HWRM shall ignore the enabled auto_XXX field. When
|
||||
* this bit is set to zero, the link shall be allowed to autoneg.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_FORCE UINT32_C(0x4)
|
||||
/*
|
||||
* When this bit is set to '1', the auto-negotiation process shall be
|
||||
* restarted on the link.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_RESTART_AUTONEG UINT32_C(0x8)
|
||||
/*
|
||||
* When this bit is set to '1', Energy Efficient Ethernet (EEE) is
|
||||
* requested to be enabled on this link. If EEE is not supported on this
|
||||
* port, then this flag shall be ignored by the HWRM.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_ENABLE UINT32_C(0x10)
|
||||
/*
|
||||
* When this bit is set to '1', Energy Efficient Ethernet (EEE) is
|
||||
* requested to be disabled on this link. If EEE is not supported on
|
||||
* this port, then this flag shall be ignored by the HWRM.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_DISABLE UINT32_C(0x20)
|
||||
/*
|
||||
* When this bit is set to '1' and EEE is enabled on this link, then TX
|
||||
* LPI is requested to be enabled on the link. If EEE is not supported
|
||||
* on this port, then this flag shall be ignored by the HWRM. If EEE is
|
||||
* disabled on this port, then this flag shall be ignored by the HWRM.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FLAGS_EEE_TX_LPI UINT32_C(0x40)
|
||||
uint32_t flags;
|
||||
|
||||
/* This bit must be '1' for the auto_mode field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_MODE UINT32_C(0x1)
|
||||
/* This bit must be '1' for the auto_duplex field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_DUPLEX UINT32_C(0x2)
|
||||
/* This bit must be '1' for the auto_pause field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_PAUSE UINT32_C(0x4)
|
||||
/*
|
||||
* This bit must be '1' for the auto_link_speed field to be configured.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED UINT32_C(0x8)
|
||||
/*
|
||||
* This bit must be '1' for the auto_link_speed_mask field to be
|
||||
* configured.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_AUTO_LINK_SPEED_MASK \
|
||||
UINT32_C(0x10)
|
||||
/* This bit must be '1' for the wirespeed field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_WIRESPEED UINT32_C(0x20)
|
||||
/* This bit must be '1' for the lpbk field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_LPBK UINT32_C(0x40)
|
||||
/* This bit must be '1' for the preemphasis field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_PREEMPHASIS UINT32_C(0x80)
|
||||
/* This bit must be '1' for the force_pause field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_FORCE_PAUSE UINT32_C(0x100)
|
||||
/*
|
||||
* This bit must be '1' for the eee_link_speed_mask field to be
|
||||
* configured.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_EEE_LINK_SPEED_MASK \
|
||||
UINT32_C(0x200)
|
||||
/* This bit must be '1' for the tx_lpi_timer field to be configured. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_ENABLES_TX_LPI_TIMER UINT32_C(0x400)
|
||||
uint32_t enables;
|
||||
|
||||
/* Port ID of port that is to be configured. */
|
||||
uint16_t port_id;
|
||||
|
||||
/*
|
||||
* This is the speed that will be used if the force bit is '1'. If
|
||||
* unsupported speed is selected, an error will be generated.
|
||||
*/
|
||||
/* 100Mb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100MB \
|
||||
(UINT32_C(0x1) << 0)
|
||||
/* 1Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_1GB \
|
||||
(UINT32_C(0xa) << 0)
|
||||
/* 2Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2GB \
|
||||
(UINT32_C(0x14) << 0)
|
||||
/* 2.5Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_2_5GB \
|
||||
(UINT32_C(0x19) << 0)
|
||||
/* 10Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10GB \
|
||||
(UINT32_C(0x64) << 0)
|
||||
/* 20Mb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_20GB \
|
||||
(UINT32_C(0xc8) << 0)
|
||||
/* 25Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_25GB \
|
||||
(UINT32_C(0xfa) << 0)
|
||||
/* 40Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_40GB \
|
||||
(UINT32_C(0x190) << 0)
|
||||
/* 50Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB \
|
||||
(UINT32_C(0x1f4) << 0)
|
||||
/* 100Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB \
|
||||
(UINT32_C(0x3e8) << 0)
|
||||
/* 10Mb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB \
|
||||
(UINT32_C(0xffff) << 0)
|
||||
uint16_t force_link_speed;
|
||||
|
||||
/*
|
||||
* This value is used to identify what autoneg mode is used when the
|
||||
* link speed is not being forced.
|
||||
*/
|
||||
/*
|
||||
* Disable autoneg or autoneg disabled. No speeds are selected.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_NONE (UINT32_C(0x0) << 0)
|
||||
/* Select all possible speeds for autoneg mode. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ALL_SPEEDS \
|
||||
(UINT32_C(0x1) << 0)
|
||||
/*
|
||||
* Select only the auto_link_speed speed for autoneg mode. This
|
||||
* mode has been DEPRECATED. An HWRM client should not use this
|
||||
* mode.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_SPEED \
|
||||
(UINT32_C(0x2) << 0)
|
||||
/*
|
||||
* Select the auto_link_speed or any speed below that speed for
|
||||
* autoneg. This mode has been DEPRECATED. An HWRM client should
|
||||
* not use this mode.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_ONE_OR_BELOW \
|
||||
(UINT32_C(0x3) << 0)
|
||||
/*
|
||||
* Select the speeds based on the corresponding link speed mask
|
||||
* value that is provided.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_MODE_SPEED_MASK \
|
||||
(UINT32_C(0x4) << 0)
|
||||
uint8_t auto_mode;
|
||||
|
||||
/*
|
||||
* This is the duplex setting that will be used if the autoneg_mode is
|
||||
* "one_speed" or "one_or_below".
|
||||
*/
|
||||
/* Half Duplex will be requested. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_HALF \
|
||||
(UINT32_C(0x0) << 0)
|
||||
/* Full duplex will be requested. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_FULL \
|
||||
(UINT32_C(0x1) << 0)
|
||||
/* Both Half and Full dupex will be requested. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_DUPLEX_BOTH \
|
||||
(UINT32_C(0x2) << 0)
|
||||
uint8_t auto_duplex;
|
||||
|
||||
/*
|
||||
* This value is used to configure the pause that will be used for
|
||||
* autonegotiation. Add text on the usage of auto_pause and force_pause.
|
||||
*/
|
||||
/*
|
||||
* When this bit is '1', Generation of tx pause messages has been
|
||||
* requested. Disabled otherwise.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX UINT32_C(0x1)
|
||||
/*
|
||||
* When this bit is '1', Reception of rx pause messages has been
|
||||
* requested. Disabled otherwise.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX UINT32_C(0x2)
|
||||
/*
|
||||
* When set to 1, the advertisement of pause is enabled. # When the
|
||||
* auto_mode is not set to none and this flag is set to 1, then the
|
||||
* auto_pause bits on this port are being advertised and autoneg pause
|
||||
* results are being interpreted. # When the auto_mode is not set to
|
||||
* none and this flag is set to 0, the pause is forced as indicated in
|
||||
* force_pause, and also advertised as auto_pause bits, but the autoneg
|
||||
* results are not interpreted since the pause configuration is being
|
||||
* forced. # When the auto_mode is set to none and this flag is set to
|
||||
* 1, auto_pause bits should be ignored and should be set to 0.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_AUTONEG_PAUSE UINT32_C(0x4)
|
||||
uint8_t auto_pause;
|
||||
|
||||
uint8_t unused_0;
|
||||
|
||||
/*
|
||||
* This is the speed that will be used if the autoneg_mode is
|
||||
* "one_speed" or "one_or_below". If an unsupported speed is selected,
|
||||
* an error will be generated.
|
||||
*/
|
||||
/* 100Mb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100MB \
|
||||
(UINT32_C(0x1) << 0)
|
||||
/* 1Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_1GB \
|
||||
(UINT32_C(0xa) << 0)
|
||||
/* 2Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2GB \
|
||||
(UINT32_C(0x14) << 0)
|
||||
/* 2.5Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_2_5GB \
|
||||
(UINT32_C(0x19) << 0)
|
||||
/* 10Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10GB \
|
||||
(UINT32_C(0x64) << 0)
|
||||
/* 20Mb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_20GB \
|
||||
(UINT32_C(0xc8) << 0)
|
||||
/* 25Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_25GB \
|
||||
(UINT32_C(0xfa) << 0)
|
||||
/* 40Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_40GB \
|
||||
(UINT32_C(0x190) << 0)
|
||||
/* 50Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB \
|
||||
(UINT32_C(0x1f4) << 0)
|
||||
/* 100Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB \
|
||||
(UINT32_C(0x3e8) << 0)
|
||||
/* 10Mb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB \
|
||||
(UINT32_C(0xffff) << 0)
|
||||
uint16_t auto_link_speed;
|
||||
|
||||
/*
|
||||
* This is a mask of link speeds that will be used if autoneg_mode is
|
||||
* "mask". If unsupported speed is enabled an error will be generated.
|
||||
*/
|
||||
/* 100Mb link speed (Half-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MBHD \
|
||||
UINT32_C(0x1)
|
||||
/* 100Mb link speed (Full-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100MB \
|
||||
UINT32_C(0x2)
|
||||
/* 1Gb link speed (Half-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GBHD \
|
||||
UINT32_C(0x4)
|
||||
/* 1Gb link speed (Full-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_1GB \
|
||||
UINT32_C(0x8)
|
||||
/* 2Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2GB \
|
||||
UINT32_C(0x10)
|
||||
/* 2.5Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_2_5GB \
|
||||
UINT32_C(0x20)
|
||||
/* 10Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10GB \
|
||||
UINT32_C(0x40)
|
||||
/* 20Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_20GB \
|
||||
UINT32_C(0x80)
|
||||
/* 25Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_25GB \
|
||||
UINT32_C(0x100)
|
||||
/* 40Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_40GB \
|
||||
UINT32_C(0x200)
|
||||
/* 50Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_50GB \
|
||||
UINT32_C(0x400)
|
||||
/* 100Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_100GB \
|
||||
UINT32_C(0x800)
|
||||
/* 10Mb link speed (Half-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MBHD \
|
||||
UINT32_C(0x1000)
|
||||
/* 10Mb link speed (Full-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
|
||||
UINT32_C(0x2000)
|
||||
uint16_t auto_link_speed_mask;
|
||||
|
||||
/* This value controls the wirespeed feature. */
|
||||
/* Wirespeed feature is disabled. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_OFF (UINT32_C(0x0) << 0)
|
||||
/* Wirespeed feature is enabled. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_WIRESPEED_ON (UINT32_C(0x1) << 0)
|
||||
uint8_t wirespeed;
|
||||
|
||||
/* This value controls the loopback setting for the PHY. */
|
||||
/* No loopback is selected. Normal operation. */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_NONE (UINT32_C(0x0) << 0)
|
||||
/*
|
||||
* The HW will be configured with local loopback such that host
|
||||
* data is sent back to the host without modification.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_LOCAL (UINT32_C(0x1) << 0)
|
||||
/*
|
||||
* The HW will be configured with remote loopback such that port
|
||||
* logic will send packets back out the transmitter that are
|
||||
* received.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_LPBK_REMOTE (UINT32_C(0x2) << 0)
|
||||
uint8_t lpbk;
|
||||
|
||||
/*
|
||||
* This value is used to configure the pause that will be used for force
|
||||
* mode.
|
||||
*/
|
||||
/*
|
||||
* When this bit is '1', Generation of tx pause messages is supported.
|
||||
* Disabled otherwise.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX UINT32_C(0x1)
|
||||
/*
|
||||
* When this bit is '1', Reception of rx pause messages is supported.
|
||||
* Disabled otherwise.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX UINT32_C(0x2)
|
||||
uint8_t force_pause;
|
||||
|
||||
uint8_t unused_1;
|
||||
|
||||
/*
|
||||
* This value controls the pre-emphasis to be used for the link. Driver
|
||||
* should not set this value (use enable.preemphasis = 0) unless driver
|
||||
* is sure of setting. Normally HWRM FW will determine proper pre-
|
||||
* emphasis.
|
||||
*/
|
||||
uint32_t preemphasis;
|
||||
|
||||
/*
|
||||
* Setting for link speed mask that is used to advertise speeds during
|
||||
* autonegotiation when EEE is enabled. This field is valid only when
|
||||
* EEE is enabled. The speeds specified in this field shall be a subset
|
||||
* of speeds specified in auto_link_speed_mask. If EEE is enabled,then
|
||||
* at least one speed shall be provided in this mask.
|
||||
*/
|
||||
/* Reserved */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD1 UINT32_C(0x1)
|
||||
/* 100Mb link speed (Full-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_100MB UINT32_C(0x2)
|
||||
/* Reserved */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD2 UINT32_C(0x4)
|
||||
/* 1Gb link speed (Full-duplex) */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_1GB UINT32_C(0x8)
|
||||
/* Reserved */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD3 \
|
||||
UINT32_C(0x10)
|
||||
/* Reserved */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_RSVD4 \
|
||||
UINT32_C(0x20)
|
||||
/* 10Gb link speed */
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_EEE_LINK_SPEED_MASK_10GB \
|
||||
UINT32_C(0x40)
|
||||
uint16_t eee_link_speed_mask;
|
||||
|
||||
uint8_t unused_2;
|
||||
uint8_t unused_3;
|
||||
|
||||
/*
|
||||
* Reuested setting of TX LPI timer in microseconds. This field is valid
|
||||
* only when EEE is enabled and TX LPI is enabled.
|
||||
*/
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_MASK \
|
||||
UINT32_C(0xffffff)
|
||||
#define HWRM_PORT_PHY_CFG_INPUT_TX_LPI_TIMER_SFT 0
|
||||
uint32_t tx_lpi_timer;
|
||||
|
||||
uint32_t unused_4;
|
||||
} __attribute__((packed));
|
||||
|
||||
/* Output (16 bytes) */
|
||||
struct hwrm_port_phy_cfg_output {
|
||||
/*
|
||||
* Pass/Fail or error type Note: receiver to verify the in parameters,
|
||||
* and fail the call with an error when appropriate
|
||||
*/
|
||||
uint16_t error_code;
|
||||
|
||||
/* This field returns the type of original request. */
|
||||
uint16_t req_type;
|
||||
|
||||
/* This field provides original sequence number of the command. */
|
||||
uint16_t seq_id;
|
||||
|
||||
/*
|
||||
* This field is the length of the response in bytes. The last byte of
|
||||
* the response is a valid flag that will read as '1' when the command
|
||||
* has been completely written to memory.
|
||||
*/
|
||||
uint16_t resp_len;
|
||||
|
||||
uint32_t unused_0;
|
||||
uint8_t unused_1;
|
||||
uint8_t unused_2;
|
||||
uint8_t unused_3;
|
||||
|
||||
/*
|
||||
* This field is used in Output records to indicate that the output is
|
||||
* completely written to RAM. This field should be read as '1' to
|
||||
* indicate that the output has been completely written. When writing a
|
||||
* command completion or response to an internal processor, the order of
|
||||
* writes has to be such that this field is written last.
|
||||
*/
|
||||
uint8_t valid;
|
||||
} __attribute__((packed));
|
||||
|
||||
/* hwrm_ver_get */
|
||||
/*
|
||||
* Description: This function is called by a driver to determine the HWRM
|
||||
|
||||
Loading…
Reference in New Issue
Block a user