e1000: minor changes
Signed-off-by: Intel
This commit is contained in:
Intel
Thomas Monjalon
parent
5037620be5
commit
1d2d65121b
@ -37,9 +37,6 @@ POSSIBILITY OF SUCH DAMAGE.
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#include "e1000_api.h"
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STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
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STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
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STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
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STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
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STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
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STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
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@ -69,7 +66,6 @@ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
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u16 *data);
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static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
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u16 data);
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static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
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static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
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static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
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STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
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@ -760,7 +756,7 @@ STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
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STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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u16 phy_data, index;
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DEBUGFUNC("e1000_get_cable_length_80003es2lan");
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@ -889,9 +885,9 @@ STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
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/* Initialize identification LED */
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ret_val = mac->ops.id_led_init(hw);
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/* An error is not fatal and we should not stop init due to this */
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if (ret_val)
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DEBUGOUT("Error initializing identification LED\n");
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/* This is not fatal and we should not stop init due to this */
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/* Disabling VLAN filtering */
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DEBUGOUT("Initializing the IEEE VLAN\n");
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@ -917,14 +913,14 @@ STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
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/* Set the transmit descriptor write-back policy */
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reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
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reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
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reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
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E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
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/* ...for both queues. */
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reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
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reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
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reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
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E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
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/* Enable retransmit on late collisions */
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@ -951,10 +947,9 @@ STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
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/* default to true to enable the MDIC W/A */
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hw->dev_spec._80003es2lan.mdic_wa_enable = true;
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ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET >>
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E1000_KMRNCTRLSTA_OFFSET_SHIFT,
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&i);
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ret_val =
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e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
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E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
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if (!ret_val) {
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if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
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E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
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@ -1028,7 +1023,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val;
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u32 ctrl_ext;
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u32 reg;
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u16 data;
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DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
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@ -1093,20 +1088,19 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
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}
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/* Bypass Rx and Tx FIFO's */
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
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E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
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E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
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reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
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data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
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E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
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if (ret_val)
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return ret_val;
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ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data);
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reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
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ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
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if (ret_val)
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return ret_val;
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data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data);
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
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if (ret_val)
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return ret_val;
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@ -1119,9 +1113,9 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
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ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
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E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
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reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
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reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
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E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
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ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
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if (ret_val)
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@ -1203,13 +1197,17 @@ STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
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reg_data);
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if (ret_val)
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return ret_val;
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ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ®_data);
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ret_val =
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e1000_read_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
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®_data);
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if (ret_val)
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return ret_val;
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reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data);
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ret_val =
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e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
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reg_data);
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if (ret_val)
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return ret_val;
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@ -1269,9 +1267,10 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
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DEBUGFUNC("e1000_configure_kmrn_for_10_100");
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reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
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reg_data);
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ret_val =
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e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
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reg_data);
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if (ret_val)
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return ret_val;
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@ -1319,8 +1318,10 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
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DEBUGFUNC("e1000_configure_kmrn_for_1000");
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reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data);
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ret_val =
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e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
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reg_data);
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if (ret_val)
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return ret_val;
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@ -1362,7 +1363,7 @@ static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
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u16 *data)
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{
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u32 kmrnctrlsta;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
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@ -1399,7 +1400,7 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
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u16 data)
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{
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u32 kmrnctrlsta;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
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@ -1425,7 +1426,7 @@ static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
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**/
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STATIC s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
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{
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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DEBUGFUNC("e1000_read_mac_addr_80003es2lan");
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@ -50,21 +50,21 @@ POSSIBILITY OF SUCH DAMAGE.
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#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
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#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
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#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
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#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */
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#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
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#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
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#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
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/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
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#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */
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#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */
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#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
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#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
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#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
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#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
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/* PHY Specific Control Register 2 (Page 0, Register 26) */
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#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Nego */
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#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */
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/* MAC Specific Control Register (Page 2, Register 21) */
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/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
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@ -49,9 +49,6 @@ POSSIBILITY OF SUCH DAMAGE.
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#include "e1000_api.h"
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STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
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STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
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STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
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STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
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STATIC void e1000_release_nvm_82571(struct e1000_hw *hw);
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STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
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@ -76,7 +73,6 @@ static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
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static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
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static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
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static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
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static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
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static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
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static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
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static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
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@ -603,16 +599,14 @@ static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
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DEBUGFUNC("e1000_get_hw_semaphore_82573");
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extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
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extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
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do {
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extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
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E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
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extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
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if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
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break;
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extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
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msec_delay(2);
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i++;
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} while (i < MDIO_OWNERSHIP_TIMEOUT);
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@ -932,9 +926,9 @@ static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
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}
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for (i = 0; i < words; i++) {
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eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
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((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
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E1000_NVM_RW_REG_START;
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eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
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((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
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E1000_NVM_RW_REG_START);
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ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
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if (ret_val)
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@ -1198,9 +1192,9 @@ STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
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/* Initialize identification LED */
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ret_val = mac->ops.id_led_init(hw);
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/* An error is not fatal and we should not stop init due to this */
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if (ret_val)
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DEBUGOUT("Error initializing identification LED\n");
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/* This is not fatal and we should not stop init due to this */
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/* Disabling VLAN filtering */
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DEBUGOUT("Initializing the IEEE VLAN\n");
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@ -1225,8 +1219,8 @@ STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
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/* Set the transmit descriptor write-back policy */
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reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
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reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
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reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
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E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
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/* ...for both queues. */
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@ -1242,9 +1236,9 @@ STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw)
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break;
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default:
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reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
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reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB |
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E1000_TXDCTL_COUNT_DESC;
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reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
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E1000_TXDCTL_FULL_TX_DESC_WB |
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E1000_TXDCTL_COUNT_DESC);
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E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
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break;
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}
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@ -1496,7 +1490,7 @@ bool e1000_check_phy_82574(struct e1000_hw *hw)
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{
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u16 status_1kbt = 0;
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u16 receive_errors = 0;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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DEBUGFUNC("e1000_check_phy_82574");
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@ -1655,13 +1649,12 @@ STATIC s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
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ctrl = E1000_READ_REG(hw, E1000_CTRL);
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status = E1000_READ_REG(hw, E1000_STATUS);
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rxcw = E1000_READ_REG(hw, E1000_RXCW);
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E1000_READ_REG(hw, E1000_RXCW);
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/* SYNCH bit and IV bit are sticky */
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usec_delay(10);
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rxcw = E1000_READ_REG(hw, E1000_RXCW);
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if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
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/* Receiver is synchronized with no invalid bits. */
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switch (mac->serdes_link_state) {
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case e1000_serdes_link_autoneg_complete:
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@ -1939,7 +1932,7 @@ STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
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DEBUGFUNC("e1000_read_mac_addr_82571");
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if (hw->mac.type == e1000_82571) {
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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/* If there's an alternate MAC address place it in RAR0
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* so that it will override the Si installed default perm
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@ -333,6 +333,7 @@ s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
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} else {
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nvm->type = e1000_nvm_flash_hw;
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}
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/* Function Pointers */
|
||||
nvm->ops.acquire = e1000_acquire_nvm_82575;
|
||||
nvm->ops.release = e1000_release_nvm_82575;
|
||||
@ -1801,15 +1802,14 @@ STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
|
||||
}
|
||||
if (ret_val != E1000_SUCCESS)
|
||||
goto out;
|
||||
|
||||
ret_val = e1000_read_sfp_data_byte(hw,
|
||||
E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
|
||||
(u8 *)eth_flags);
|
||||
if (ret_val != E1000_SUCCESS)
|
||||
goto out;
|
||||
/*
|
||||
* Check if there is some SFP
|
||||
* module plugged and powered
|
||||
*/
|
||||
|
||||
/* Check if there is some SFP module plugged and powered */
|
||||
if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
|
||||
(tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
|
||||
dev_spec->module_plugged = true;
|
||||
@ -1822,9 +1822,9 @@ STATIC s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
|
||||
dev_spec->sgmii_active = true;
|
||||
hw->phy.media_type = e1000_media_type_copper;
|
||||
} else {
|
||||
hw->phy.media_type = e1000_media_type_unknown;
|
||||
DEBUGOUT("PHY module has not been recognized\n");
|
||||
goto out;
|
||||
hw->phy.media_type = e1000_media_type_unknown;
|
||||
DEBUGOUT("PHY module has not been recognized\n");
|
||||
goto out;
|
||||
}
|
||||
} else {
|
||||
hw->phy.media_type = e1000_media_type_unknown;
|
||||
|
||||
@ -882,8 +882,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
E1000_IMS_RXDMT0 | \
|
||||
E1000_IMS_RXSEQ)
|
||||
|
||||
/*
|
||||
* This defines the bits that are set in the Interrupt Mask
|
||||
/* This defines the bits that are set in the Interrupt Mask
|
||||
* Set/Read Register. Each bit is documented below:
|
||||
* o RXT0 = Receiver Timer Interrupt (ring 0)
|
||||
* o TXDW = Transmit Descriptor Written Back
|
||||
@ -1030,8 +1029,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
|
||||
#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
|
||||
|
||||
/* Receive Address */
|
||||
/*
|
||||
/* Receive Address
|
||||
* Number of high/low register pairs in the RAR. The RAR (Receive Address
|
||||
* Registers) holds the directed and multicast addresses that we monitor.
|
||||
* Technically, we have 16 spots. However, we reserve one of these spots
|
||||
@ -1558,8 +1556,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
|
||||
#define MAX_PHY_MULTI_PAGE_REG 0xF
|
||||
|
||||
/* Bit definitions for valid PHY IDs. */
|
||||
/*
|
||||
/* Bit definitions for valid PHY IDs.
|
||||
* I = Integrated
|
||||
* E = External
|
||||
*/
|
||||
@ -1632,8 +1629,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
|
||||
#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
|
||||
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
|
||||
/*
|
||||
* 0 = <50M
|
||||
/* 0 = <50M
|
||||
* 1 = 50-80M
|
||||
* 2 = 80-110M
|
||||
* 3 = 110-140M
|
||||
@ -1660,8 +1656,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
* within 1ms in 1000BASE-T
|
||||
*/
|
||||
#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
|
||||
/*
|
||||
* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
/* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
* are the master
|
||||
*/
|
||||
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
|
||||
@ -1669,8 +1664,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
|
||||
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
|
||||
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
|
||||
/*
|
||||
* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
/* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
* are the slave
|
||||
*/
|
||||
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
|
||||
@ -1697,8 +1691,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
/* I347AT4 Extended PHY Specific Control Register */
|
||||
|
||||
/*
|
||||
* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
/* Number of times we will attempt to autonegotiate before downshifting if we
|
||||
* are the master
|
||||
*/
|
||||
#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800
|
||||
@ -1735,8 +1728,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
/* BME1000 PHY Specific Control Register */
|
||||
#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
|
||||
|
||||
/*
|
||||
* Bits...
|
||||
/* Bits...
|
||||
* 15-5: page
|
||||
* 4-0: register offset
|
||||
*/
|
||||
@ -1881,7 +1873,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define E1000_PROXYFC_ARP_DIRECTED 0x00000020 /* Directed ARP Proxy Ena */
|
||||
#define E1000_PROXYFC_IPV4 0x00000040 /* Directed IPv4 Enable */
|
||||
#define E1000_PROXYFC_IPV6 0x00000080 /* Directed IPv6 Enable */
|
||||
#define E1000_PROXYFC_NS 0x00000200 /* IPv4 NBRHD Solicitation */
|
||||
#define E1000_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */
|
||||
#define E1000_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Ena */
|
||||
/* Proxy Status */
|
||||
#define E1000_PROXYS_CLEAR 0xFFFFFFFF /* Clear */
|
||||
|
||||
@ -122,7 +122,6 @@ struct e1000_hw;
|
||||
#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
|
||||
#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
|
||||
#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
|
||||
|
||||
#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
|
||||
#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
|
||||
#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
|
||||
@ -166,6 +165,7 @@ struct e1000_hw;
|
||||
#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
|
||||
#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
|
||||
#define E1000_DEV_ID_DH89XXCC_SFP 0x0440
|
||||
|
||||
#define E1000_REVISION_0 0
|
||||
#define E1000_REVISION_1 1
|
||||
#define E1000_REVISION_2 2
|
||||
@ -653,13 +653,13 @@ struct e1000_host_mng_command_info {
|
||||
#include "e1000_manage.h"
|
||||
#include "e1000_mbx.h"
|
||||
|
||||
/* Function pointers for the MAC. */
|
||||
struct e1000_mac_operations {
|
||||
/* Function pointers for the MAC. */
|
||||
s32 (*init_params)(struct e1000_hw *);
|
||||
s32 (*id_led_init)(struct e1000_hw *);
|
||||
s32 (*blink_led)(struct e1000_hw *);
|
||||
bool (*check_mng_mode)(struct e1000_hw *);
|
||||
s32 (*check_for_link)(struct e1000_hw *);
|
||||
bool (*check_mng_mode)(struct e1000_hw *hw);
|
||||
s32 (*cleanup_led)(struct e1000_hw *);
|
||||
void (*clear_hw_cntrs)(struct e1000_hw *);
|
||||
void (*clear_vfta)(struct e1000_hw *);
|
||||
@ -690,8 +690,7 @@ struct e1000_mac_operations {
|
||||
void (*release_swfw_sync)(struct e1000_hw *, u16);
|
||||
};
|
||||
|
||||
/*
|
||||
* When to use various PHY register access functions:
|
||||
/* When to use various PHY register access functions:
|
||||
*
|
||||
* Func Caller
|
||||
* Function Does Does When to use
|
||||
@ -733,6 +732,7 @@ struct e1000_phy_operations {
|
||||
s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
|
||||
};
|
||||
|
||||
/* Function pointers for the NVM. */
|
||||
struct e1000_nvm_operations {
|
||||
s32 (*init_params)(struct e1000_hw *);
|
||||
s32 (*acquire)(struct e1000_hw *);
|
||||
@ -917,7 +917,7 @@ struct e1000_shadow_ram {
|
||||
bool modified;
|
||||
};
|
||||
|
||||
#define E1000_SHADOW_RAM_WORDS 2048
|
||||
#define E1000_SHADOW_RAM_WORDS 2048
|
||||
|
||||
struct e1000_dev_spec_ich8lan {
|
||||
bool kmrn_lock_loss_workaround_enabled;
|
||||
|
||||
@ -62,10 +62,6 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
#include "e1000_api.h"
|
||||
|
||||
STATIC s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
|
||||
STATIC void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw);
|
||||
@ -106,8 +102,6 @@ STATIC s32 e1000_led_on_pchlan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_led_off_pchlan(struct e1000_hw *hw);
|
||||
STATIC void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
|
||||
static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
|
||||
static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
|
||||
static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
|
||||
static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
|
||||
@ -118,15 +112,9 @@ STATIC s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
|
||||
u32 offset, u16 *data);
|
||||
static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
|
||||
u32 offset, u8 byte);
|
||||
STATIC s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
|
||||
u32 offset, u8 data);
|
||||
static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
|
||||
u8 size, u16 data);
|
||||
STATIC s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
|
||||
STATIC void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
|
||||
static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw);
|
||||
STATIC void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
|
||||
STATIC s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
|
||||
STATIC void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
|
||||
@ -329,7 +317,7 @@ static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
|
||||
STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
|
||||
{
|
||||
struct e1000_phy_info *phy = &hw->phy;
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
s32 ret_val;
|
||||
|
||||
DEBUGFUNC("e1000_init_phy_params_pchlan");
|
||||
|
||||
@ -370,8 +358,8 @@ STATIC s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
|
||||
break;
|
||||
/* fall-through */
|
||||
case e1000_pch2lan:
|
||||
/*
|
||||
* In case the PHY needs to be in mdio slow mode,
|
||||
case e1000_pch_lpt:
|
||||
/* In case the PHY needs to be in mdio slow mode,
|
||||
* set slow mode and try to get the PHY id again.
|
||||
*/
|
||||
ret_val = e1000_set_mdio_slow_mode_hv(hw);
|
||||
@ -539,8 +527,8 @@ STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
|
||||
/* find total size of the NVM, then cut in half since the total
|
||||
* size represents two separate NVM banks.
|
||||
*/
|
||||
nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
|
||||
<< FLASH_SECTOR_ADDR_SHIFT;
|
||||
nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
|
||||
<< FLASH_SECTOR_ADDR_SHIFT);
|
||||
nvm->flash_bank_size /= 2;
|
||||
/* Adjust to word count */
|
||||
nvm->flash_bank_size /= sizeof(u16);
|
||||
@ -686,7 +674,7 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
|
||||
STATIC s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
|
||||
u16 *data, bool read)
|
||||
{
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
s32 ret_val;
|
||||
|
||||
DEBUGFUNC("__e1000_access_emi_reg_locked");
|
||||
|
||||
@ -1096,9 +1084,9 @@ STATIC bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
|
||||
|
||||
fwsm = E1000_READ_REG(hw, E1000_FWSM);
|
||||
|
||||
return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
|
||||
((fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
|
||||
return ((fwsm & E1000_ICH_FWSM_FW_VALID) &&
|
||||
((fwsm & E1000_FWSM_MODE_MASK) ==
|
||||
(E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)));
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1219,7 +1207,7 @@ STATIC s32 e1000_write_smbus_addr(struct e1000_hw *hw)
|
||||
u32 strap = E1000_READ_REG(hw, E1000_STRAP);
|
||||
u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
|
||||
E1000_STRAP_SMT_FREQ_SHIFT;
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
s32 ret_val;
|
||||
|
||||
strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
|
||||
|
||||
@ -1402,9 +1390,9 @@ STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
|
||||
if (ret_val)
|
||||
goto release;
|
||||
|
||||
status_reg &= BM_CS_STATUS_LINK_UP |
|
||||
BM_CS_STATUS_RESOLVED |
|
||||
BM_CS_STATUS_SPEED_MASK;
|
||||
status_reg &= (BM_CS_STATUS_LINK_UP |
|
||||
BM_CS_STATUS_RESOLVED |
|
||||
BM_CS_STATUS_SPEED_MASK);
|
||||
|
||||
if (status_reg == (BM_CS_STATUS_LINK_UP |
|
||||
BM_CS_STATUS_RESOLVED |
|
||||
@ -1418,9 +1406,9 @@ STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
|
||||
if (ret_val)
|
||||
goto release;
|
||||
|
||||
status_reg &= HV_M_STATUS_LINK_UP |
|
||||
HV_M_STATUS_AUTONEG_COMPLETE |
|
||||
HV_M_STATUS_SPEED_MASK;
|
||||
status_reg &= (HV_M_STATUS_LINK_UP |
|
||||
HV_M_STATUS_AUTONEG_COMPLETE |
|
||||
HV_M_STATUS_SPEED_MASK);
|
||||
|
||||
if (status_reg == (HV_M_STATUS_LINK_UP |
|
||||
HV_M_STATUS_AUTONEG_COMPLETE |
|
||||
@ -1462,7 +1450,7 @@ STATIC s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
|
||||
**/
|
||||
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
|
||||
{
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
s32 ret_val;
|
||||
u32 ctrl_reg = 0;
|
||||
u32 ctrl_ext = 0;
|
||||
u32 reg = 0;
|
||||
@ -2176,7 +2164,7 @@ STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
|
||||
**/
|
||||
STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
|
||||
{
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
s32 ret_val;
|
||||
u16 oem_reg;
|
||||
|
||||
DEBUGFUNC("e1000_set_lplu_state_pchlan");
|
||||
@ -2687,11 +2675,11 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
|
||||
|
||||
DEBUGFUNC("e1000_read_flash_data_ich8lan");
|
||||
|
||||
if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
|
||||
if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
|
||||
return -E1000_ERR_NVM;
|
||||
|
||||
flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
|
||||
hw->nvm.flash_base_addr;
|
||||
flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
|
||||
hw->nvm.flash_base_addr);
|
||||
|
||||
do {
|
||||
usec_delay(1);
|
||||
@ -2708,8 +2696,9 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
|
||||
|
||||
E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
|
||||
|
||||
ret_val = e1000_flash_cycle_ich8lan(hw,
|
||||
ICH_FLASH_READ_COMMAND_TIMEOUT);
|
||||
ret_val =
|
||||
e1000_flash_cycle_ich8lan(hw,
|
||||
ICH_FLASH_READ_COMMAND_TIMEOUT);
|
||||
|
||||
/* Check if FCERR is set to 1, if set to 1, clear it
|
||||
* and try the whole sequence a few more times, else
|
||||
@ -3008,8 +2997,8 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
|
||||
offset > ICH_FLASH_LINEAR_ADDR_MASK)
|
||||
return -E1000_ERR_NVM;
|
||||
|
||||
flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
|
||||
hw->nvm.flash_base_addr;
|
||||
flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
|
||||
hw->nvm.flash_base_addr);
|
||||
|
||||
do {
|
||||
usec_delay(1);
|
||||
@ -3036,8 +3025,9 @@ static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
|
||||
/* check if FCERR is set to 1 , if set to 1, clear it
|
||||
* and try the whole sequence a few more times else done
|
||||
*/
|
||||
ret_val = e1000_flash_cycle_ich8lan(hw,
|
||||
ICH_FLASH_WRITE_COMMAND_TIMEOUT);
|
||||
ret_val =
|
||||
e1000_flash_cycle_ich8lan(hw,
|
||||
ICH_FLASH_WRITE_COMMAND_TIMEOUT);
|
||||
if (ret_val == E1000_SUCCESS)
|
||||
break;
|
||||
|
||||
@ -3173,8 +3163,10 @@ STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
|
||||
flash_linear_addr = hw->nvm.flash_base_addr;
|
||||
flash_linear_addr += (bank) ? flash_bank_size : 0;
|
||||
|
||||
for (j = 0; j < iteration ; j++) {
|
||||
for (j = 0; j < iteration; j++) {
|
||||
do {
|
||||
u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
|
||||
|
||||
/* Steps */
|
||||
ret_val = e1000_flash_cycle_init_ich8lan(hw);
|
||||
if (ret_val)
|
||||
@ -3197,8 +3189,7 @@ STATIC s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
|
||||
E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
|
||||
flash_linear_addr);
|
||||
|
||||
ret_val = e1000_flash_cycle_ich8lan(hw,
|
||||
ICH_FLASH_ERASE_COMMAND_TIMEOUT);
|
||||
ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
|
||||
if (ret_val == E1000_SUCCESS)
|
||||
break;
|
||||
|
||||
@ -3488,9 +3479,9 @@ STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
|
||||
|
||||
/* Initialize identification LED */
|
||||
ret_val = mac->ops.id_led_init(hw);
|
||||
/* An error is not fatal and we should not stop init due to this */
|
||||
if (ret_val)
|
||||
DEBUGOUT("Error initializing identification LED\n");
|
||||
/* This is not fatal and we should not stop init due to this */
|
||||
|
||||
/* Setup the receive address. */
|
||||
e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
|
||||
@ -3518,16 +3509,16 @@ STATIC s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
|
||||
|
||||
/* Set the transmit descriptor write-back policy for both queues */
|
||||
txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
|
||||
txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
|
||||
E1000_TXDCTL_FULL_TX_DESC_WB;
|
||||
txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
|
||||
E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
|
||||
txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
|
||||
E1000_TXDCTL_FULL_TX_DESC_WB);
|
||||
txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
|
||||
E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
|
||||
E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
|
||||
txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
|
||||
txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
|
||||
E1000_TXDCTL_FULL_TX_DESC_WB;
|
||||
txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
|
||||
E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
|
||||
txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
|
||||
E1000_TXDCTL_FULL_TX_DESC_WB);
|
||||
txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
|
||||
E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
|
||||
E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
|
||||
|
||||
/* ICH8 has opposite polarity of no_snoop bits.
|
||||
@ -4010,6 +4001,7 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
|
||||
|
||||
phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
|
||||
phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
|
||||
|
||||
if (hw->phy.type == e1000_phy_i217) {
|
||||
u16 phy_reg;
|
||||
|
||||
@ -4048,7 +4040,6 @@ void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
|
||||
*/
|
||||
if (!(E1000_READ_REG(hw, E1000_FWSM) &
|
||||
E1000_ICH_FWSM_FW_VALID)) {
|
||||
|
||||
/* Enable proxy to reset only on power good. */
|
||||
hw->phy.ops.read_reg_locked(hw, I217_PROXY_CTRL,
|
||||
&phy_reg);
|
||||
|
||||
@ -62,11 +62,11 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
#define ICH_FLASH_REG_MAPSIZE 0x00A0
|
||||
|
||||
#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
|
||||
#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
|
||||
#define E1000_ICH_FWSM_DISSW 0x10000000 /* FW Disables SW Writes */
|
||||
/* FW established a valid mode */
|
||||
#define E1000_ICH_FWSM_FW_VALID 0x00008000
|
||||
#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
|
||||
#define E1000_ICH_FWSM_FW_VALID 0x00008000
|
||||
#define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */
|
||||
#define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000
|
||||
|
||||
#define E1000_ICH_MNG_IAMT_MODE 0x2
|
||||
@ -104,7 +104,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004
|
||||
|
||||
#define E1000_FEXTNVM_SW_CONFIG 1
|
||||
#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
|
||||
#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */
|
||||
|
||||
#define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */
|
||||
#define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000
|
||||
@ -122,8 +122,8 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define PHY_PAGE_SHIFT 5
|
||||
#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
|
||||
((reg) & MAX_PHY_REG_ADDRESS))
|
||||
#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
|
||||
#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
|
||||
#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
|
||||
#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
|
||||
#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
|
||||
#define IGP3_PM_CTRL PHY_REG(769, 20) /* Power Management Control */
|
||||
|
||||
@ -170,19 +170,20 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
|
||||
#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
|
||||
#define HV_STATS_PAGE 778
|
||||
#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */
|
||||
/* Half-duplex collision counts */
|
||||
#define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */
|
||||
#define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17)
|
||||
#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */
|
||||
#define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */
|
||||
#define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19)
|
||||
#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */
|
||||
#define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */
|
||||
#define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21)
|
||||
#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */
|
||||
#define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */
|
||||
#define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24)
|
||||
#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */
|
||||
#define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */
|
||||
#define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26)
|
||||
#define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */
|
||||
#define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28)
|
||||
#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */
|
||||
#define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */
|
||||
#define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30)
|
||||
|
||||
#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
|
||||
@ -262,8 +263,8 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */
|
||||
#define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */
|
||||
#define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */
|
||||
#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */
|
||||
#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */
|
||||
#define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */
|
||||
#define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */
|
||||
#define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */
|
||||
#define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */
|
||||
#define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */
|
||||
|
||||
@ -387,7 +387,7 @@ void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
|
||||
s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
|
||||
{
|
||||
u32 i;
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
s32 ret_val;
|
||||
u16 offset, nvm_alt_mac_addr_offset, nvm_data;
|
||||
u8 alt_mac_addr[ETH_ADDR_LEN];
|
||||
|
||||
@ -1498,10 +1498,9 @@ s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
|
||||
* has completed, and if so, how the PHY and link partner has
|
||||
* flow control configured.
|
||||
*/
|
||||
if ((hw->phy.media_type == e1000_media_type_internal_serdes)
|
||||
&& mac->autoneg) {
|
||||
/*
|
||||
* Read the PCS_LSTS and check to see if AutoNeg
|
||||
if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
|
||||
mac->autoneg) {
|
||||
/* Read the PCS_LSTS and check to see if AutoNeg
|
||||
* has completed.
|
||||
*/
|
||||
pcs_status_reg = E1000_READ_REG(hw, E1000_PCS_LSTAT);
|
||||
|
||||
@ -34,10 +34,6 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#ifndef _E1000_MAC_H_
|
||||
#define _E1000_MAC_H_
|
||||
|
||||
/*
|
||||
* Functions that should not be called directly from drivers but can be used
|
||||
* by other files in this 'shared code'
|
||||
*/
|
||||
void e1000_init_mac_ops_generic(struct e1000_hw *hw);
|
||||
void e1000_null_mac_generic(struct e1000_hw *hw);
|
||||
s32 e1000_null_ops_generic(struct e1000_hw *hw);
|
||||
|
||||
@ -373,7 +373,7 @@ bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
|
||||
return true;
|
||||
} else if ((manc & E1000_MANC_SMBUS_EN) &&
|
||||
!(manc & E1000_MANC_ASF_EN)) {
|
||||
return true;
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
|
||||
@ -33,7 +33,6 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
#include "e1000_api.h"
|
||||
|
||||
static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
|
||||
STATIC s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
|
||||
u16 *data, bool read, bool page_set);
|
||||
STATIC u32 e1000_get_phy_addr_for_hv_page(u32 page);
|
||||
@ -2176,9 +2175,9 @@ s32 e1000_check_polarity_m88(struct e1000_hw *hw)
|
||||
ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
|
||||
|
||||
if (!ret_val)
|
||||
phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
|
||||
? e1000_rev_polarity_reversed
|
||||
: e1000_rev_polarity_normal;
|
||||
phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
|
||||
? e1000_rev_polarity_reversed
|
||||
: e1000_rev_polarity_normal);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
@ -2222,9 +2221,9 @@ s32 e1000_check_polarity_igp(struct e1000_hw *hw)
|
||||
ret_val = phy->ops.read_reg(hw, offset, &data);
|
||||
|
||||
if (!ret_val)
|
||||
phy->cable_polarity = (data & mask)
|
||||
? e1000_rev_polarity_reversed
|
||||
: e1000_rev_polarity_normal;
|
||||
phy->cable_polarity = ((data & mask)
|
||||
? e1000_rev_polarity_reversed
|
||||
: e1000_rev_polarity_normal);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
@ -2256,9 +2255,9 @@ s32 e1000_check_polarity_ife(struct e1000_hw *hw)
|
||||
ret_val = phy->ops.read_reg(hw, offset, &phy_data);
|
||||
|
||||
if (!ret_val)
|
||||
phy->cable_polarity = (phy_data & mask)
|
||||
phy->cable_polarity = ((phy_data & mask)
|
||||
? e1000_rev_polarity_reversed
|
||||
: e1000_rev_polarity_normal;
|
||||
: e1000_rev_polarity_normal);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
@ -2374,8 +2373,8 @@ s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
|
||||
M88E1000_PSSR_CABLE_LENGTH_SHIFT;
|
||||
index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
|
||||
M88E1000_PSSR_CABLE_LENGTH_SHIFT);
|
||||
|
||||
if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
|
||||
return -E1000_ERR_PHY;
|
||||
@ -2535,8 +2534,8 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
|
||||
* that can be put into the lookup table to obtain the
|
||||
* approximate cable length.
|
||||
*/
|
||||
cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
|
||||
IGP02E1000_AGC_LENGTH_MASK;
|
||||
cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
|
||||
IGP02E1000_AGC_LENGTH_MASK);
|
||||
|
||||
/* Array index bound check. */
|
||||
if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
|
||||
@ -2559,8 +2558,8 @@ s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
|
||||
agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
|
||||
|
||||
/* Calculate cable length with the error range of +/- 10 meters. */
|
||||
phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
|
||||
(agc_value - IGP02E1000_AGC_RANGE) : 0;
|
||||
phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
|
||||
(agc_value - IGP02E1000_AGC_RANGE) : 0);
|
||||
phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
|
||||
|
||||
phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
|
||||
@ -2744,9 +2743,9 @@ s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
|
||||
return ret_val;
|
||||
} else {
|
||||
/* Polarity is forced */
|
||||
phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
|
||||
? e1000_rev_polarity_reversed
|
||||
: e1000_rev_polarity_normal;
|
||||
phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
|
||||
? e1000_rev_polarity_reversed
|
||||
: e1000_rev_polarity_normal);
|
||||
}
|
||||
|
||||
ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
|
||||
@ -3202,7 +3201,6 @@ s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
|
||||
hw->phy.addr = 1;
|
||||
|
||||
if (offset > MAX_PHY_MULTI_PAGE_REG) {
|
||||
|
||||
/* Page is shifted left, PHY expects (page x 32) */
|
||||
ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
|
||||
page);
|
||||
@ -3332,7 +3330,7 @@ s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
|
||||
**/
|
||||
s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
|
||||
{
|
||||
s32 ret_val = E1000_SUCCESS;
|
||||
s32 ret_val;
|
||||
|
||||
DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
|
||||
|
||||
@ -3752,14 +3750,14 @@ STATIC s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
|
||||
u16 *data, bool read)
|
||||
{
|
||||
s32 ret_val;
|
||||
u32 addr_reg = 0;
|
||||
u32 data_reg = 0;
|
||||
u32 addr_reg;
|
||||
u32 data_reg;
|
||||
|
||||
DEBUGFUNC("e1000_access_phy_debug_regs_hv");
|
||||
|
||||
/* This takes care of the difference with desktop vs mobile phy */
|
||||
addr_reg = (hw->phy.type == e1000_phy_82578) ?
|
||||
I82578_ADDR_REG : I82577_ADDR_REG;
|
||||
addr_reg = ((hw->phy.type == e1000_phy_82578) ?
|
||||
I82578_ADDR_REG : I82577_ADDR_REG);
|
||||
data_reg = addr_reg + 1;
|
||||
|
||||
/* All operations in this function are phy address 2 */
|
||||
@ -3815,8 +3813,8 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
|
||||
BM_CS_STATUS_SPEED_MASK;
|
||||
data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
|
||||
BM_CS_STATUS_SPEED_MASK);
|
||||
|
||||
if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
|
||||
BM_CS_STATUS_SPEED_1000))
|
||||
@ -3826,8 +3824,8 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
|
||||
|
||||
/* flush the packets in the fifo buffer */
|
||||
ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
|
||||
HV_MUX_DATA_CTRL_GEN_TO_MAC |
|
||||
HV_MUX_DATA_CTRL_FORCE_SPEED);
|
||||
(HV_MUX_DATA_CTRL_GEN_TO_MAC |
|
||||
HV_MUX_DATA_CTRL_FORCE_SPEED));
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
@ -3854,9 +3852,9 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
|
||||
ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
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||||
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||||
if (!ret_val)
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||||
phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
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||||
? e1000_rev_polarity_reversed
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||||
: e1000_rev_polarity_normal;
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||||
phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
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||||
? e1000_rev_polarity_reversed
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||||
: e1000_rev_polarity_normal);
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||||
|
||||
return ret_val;
|
||||
}
|
||||
@ -3991,8 +3989,8 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
|
||||
length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
|
||||
I82577_DSTATUS_CABLE_LENGTH_SHIFT;
|
||||
length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
|
||||
I82577_DSTATUS_CABLE_LENGTH_SHIFT);
|
||||
|
||||
if (length == E1000_CABLE_LENGTH_UNDEFINED)
|
||||
ret_val = -E1000_ERR_PHY;
|
||||
|
||||
@ -173,7 +173,7 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
#define I82577_ADDR_REG 16
|
||||
#define I82577_CFG_REG 22
|
||||
#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
|
||||
#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
|
||||
#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */
|
||||
#define I82577_CTRL_REG 23
|
||||
|
||||
/* 82577 specific PHY registers */
|
||||
@ -253,7 +253,7 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
#define IGP02E1000_PHY_AGC_C 0x14B1
|
||||
#define IGP02E1000_PHY_AGC_D 0x18B1
|
||||
|
||||
#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */
|
||||
#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */
|
||||
#define IGP02E1000_AGC_LENGTH_MASK 0x7F
|
||||
#define IGP02E1000_AGC_RANGE 15
|
||||
|
||||
@ -282,8 +282,8 @@ s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
|
||||
#define E1000_KMRNCTRLSTA_K0_100_EN 0x2000 /* ena K0s mode for 10/100 lnk */
|
||||
|
||||
#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
|
||||
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */
|
||||
#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
|
||||
#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */
|
||||
#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */
|
||||
#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
|
||||
|
||||
/* IFE PHY Extended Status Control */
|
||||
|
||||
@ -71,7 +71,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */
|
||||
#define E1000_SVCR 0x000F0
|
||||
#define E1000_SVT 0x000F4
|
||||
#define E1000_LPIC 0x000FC /* Low Power IDLE control */
|
||||
#define E1000_LPIC 0x000FC /* Low Power IDLE control */
|
||||
#define E1000_RCTL 0x00100 /* Rx Control - RW */
|
||||
#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
|
||||
#define E1000_TXCW 0x00178 /* Tx Configuration Word - RW */
|
||||
@ -202,8 +202,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
/* Queues packet buffer size masks where _n can be 0-3 and _s 0-63 [kB] */
|
||||
#define E1000_I210_TXPBS_SIZE(_n, _s) ((_s) << (6 * _n))
|
||||
|
||||
/*
|
||||
* Convenience macros
|
||||
/* Convenience macros
|
||||
*
|
||||
* Note: "_n" is the queue number of the register to be written to.
|
||||
*
|
||||
@ -415,8 +414,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
||||
#define E1000_LSECTXKEY1(_n) (0x0B030 + (0x04 * (_n)))
|
||||
#define E1000_LSECRXSA(_n) (0x0B310 + (0x04 * (_n))) /* Rx SAs - RW */
|
||||
#define E1000_LSECRXPN(_n) (0x0B330 + (0x04 * (_n))) /* Rx SAs - RW */
|
||||
/*
|
||||
* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
|
||||
/* LinkSec Rx Keys - where _n is the SA no. and _m the 4 dwords of the 128 bit
|
||||
* key - RW.
|
||||
*/
|
||||
#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user