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e1000: support I217 and I218 devices

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Modified driver and eal code to support I217 and I218 Intel NICs.

Compiled and tested (via testpmd) on Ubuntu 14.04 for target
	x86_64-native-linuxapp-gcc
Compiled for target x86_64-native-linuxapp-clang

Signed-off-by: Ravi Kerur <rkerur@gmail.com>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
This commit is contained in:
Ravi Kerur 2016-03-02 05:59:34 -08:00 committed by Thomas Monjalon
parent aba3129852
commit 1da352d62e
3 changed files with 61 additions and 6 deletions
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26
drivers/net/e1000/base/e1000_osdep.h
View File

@ -96,21 +96,35 @@ typedef int bool;
#define E1000_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
#define E1000_PCI_REG16(reg) (*((volatile uint16_t *)(reg)))
#define E1000_PCI_REG_WRITE(reg, value) do { \
E1000_PCI_REG((reg)) = (rte_cpu_to_le_32(value)); \
} while (0)
#define E1000_PCI_REG_WRITE16(reg, value) do { \
E1000_PCI_REG16((reg)) = (rte_cpu_to_le_16(value)); \
} while (0)
#define E1000_PCI_REG_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
#define E1000_PCI_REG_ARRAY_ADDR(hw, reg, index) \
E1000_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
static inline uint32_t e1000_read_addr(volatile void* addr)
#define E1000_PCI_REG_FLASH_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->flash_address + (reg)))
static inline uint32_t e1000_read_addr(volatile void *addr)
{
return rte_le_to_cpu_32(E1000_PCI_REG(addr));
}
static inline uint16_t e1000_read_addr16(volatile void *addr)
{
return rte_le_to_cpu_16(E1000_PCI_REG16(addr));
}
/* Necessary defines */
#define E1000_MRQC_ENABLE_MASK 0x00000007
#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
@ -155,20 +169,20 @@ static inline uint32_t e1000_read_addr(volatile void* addr)
E1000_WRITE_REG(hw, reg, value)
/*
* Not implemented.
* Tested on I217/I218 chipset.
*/
#define E1000_READ_FLASH_REG(hw, reg) \
(E1000_ACCESS_PANIC(E1000_READ_FLASH_REG, hw, reg, 0), 0)
e1000_read_addr(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
#define E1000_READ_FLASH_REG16(hw, reg) \
(E1000_ACCESS_PANIC(E1000_READ_FLASH_REG16, hw, reg, 0), 0)
e1000_read_addr16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)))
#define E1000_WRITE_FLASH_REG(hw, reg, value) \
E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG, hw, reg, value)
E1000_PCI_REG_WRITE(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
#define E1000_WRITE_FLASH_REG16(hw, reg, value) \
E1000_ACCESS_PANIC(E1000_WRITE_FLASH_REG16, hw, reg, value)
E1000_PCI_REG_WRITE16(E1000_PCI_REG_FLASH_ADDR((hw), (reg)), (value))
#define STATIC static

32
drivers/net/e1000/em_ethdev.c
View File

@ -231,6 +231,32 @@ rte_em_dev_atomic_write_link_status(struct rte_eth_dev *dev,
return 0;
}
/**
* eth_em_dev_is_ich8 - Check for ICH8 device
* @hw: pointer to the HW structure
*
* return TRUE for ICH8, otherwise FALSE
**/
static bool
eth_em_dev_is_ich8(struct e1000_hw *hw)
{
DEBUGFUNC("eth_em_dev_is_ich8");
switch (hw->device_id) {
case E1000_DEV_ID_PCH_LPT_I217_LM:
case E1000_DEV_ID_PCH_LPT_I217_V:
case E1000_DEV_ID_PCH_LPTLP_I218_LM:
case E1000_DEV_ID_PCH_LPTLP_I218_V:
case E1000_DEV_ID_PCH_I218_V2:
case E1000_DEV_ID_PCH_I218_LM2:
case E1000_DEV_ID_PCH_I218_V3:
case E1000_DEV_ID_PCH_I218_LM3:
return 1;
default:
return 0;
}
}
static int
eth_em_dev_init(struct rte_eth_dev *eth_dev)
{
@ -265,6 +291,8 @@ eth_em_dev_init(struct rte_eth_dev *eth_dev)
adapter->stopped = 0;
/* For ICH8 support we'll need to map the flash memory BAR */
if (eth_em_dev_is_ich8(hw))
hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
em_hw_init(hw) != 0) {
@ -490,6 +518,7 @@ em_set_pba(struct e1000_hw *hw)
break;
case e1000_pchlan:
case e1000_pch2lan:
case e1000_pch_lpt:
pba = E1000_PBA_26K;
break;
default:
@ -798,6 +827,8 @@ em_hardware_init(struct e1000_hw *hw)
hw->fc.low_water = 0x5048;
hw->fc.pause_time = 0x0650;
hw->fc.refresh_time = 0x0400;
} else if (hw->mac.type == e1000_pch_lpt) {
hw->fc.requested_mode = e1000_fc_full;
}
diag = e1000_init_hw(hw);
@ -969,6 +1000,7 @@ em_get_max_pktlen(const struct e1000_hw *hw)
case e1000_ich9lan:
case e1000_ich10lan:
case e1000_pch2lan:
case e1000_pch_lpt:
case e1000_82574:
case e1000_80003es2lan: /* 9K Jumbo Frame size */
case e1000_82583:

9
lib/librte_eal/common/include/rte_pci_dev_ids.h
View File

@ -310,6 +310,15 @@ RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82573L)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574L)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82574LA)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_82583V)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_LM)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPT_I217_V)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_LM2)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_V2)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_LM3)
RTE_PCI_DEV_ID_DECL_EM(PCI_VENDOR_ID_INTEL, E1000_DEV_ID_PCH_I218_V3)
/******************** Physical IGB devices from e1000_hw.h ********************/