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net/sfc/base: separate limitations on Tx DMA descriptors

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Siena has limitation on maximum byte count and 4k boundary crosssing
(which is stricter than maximum byte count).
EF10 has limitation on maximum byte count only.

Fixes: f7dc06bf35 ("net/sfc/base: import 5xxx/6xxx family support")
Fixes: e7cd430c86 ("net/sfc/base: import SFN7xxx family support")
Fixes: 94190e3543 ("net/sfc/base: import SFN8xxx family support")

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
This commit is contained in:
Andrew Rybchenko 2017-03-06 13:05:08 +00:00 committed by Ferruh Yigit
parent 45290ddae8
commit 1e43fe3cb4
6 changed files with 36 additions and 8 deletions
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9
drivers/net/sfc/base/ef10_tx.c
View File

@ -435,8 +435,9 @@ ef10_tx_qpost(
size_t offset;
efx_qword_t qword;
/* Fragments must not span 4k boundaries. */
EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= (addr + size));
/* No limitations on boundary crossing */
EFSYS_ASSERT(size <=
etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
id = added++ & etp->et_mask;
offset = id * sizeof (efx_qword_t);
@ -551,8 +552,8 @@ ef10_tx_qdesc_dma_create(
__in boolean_t eop,
__out efx_desc_t *edp)
{
/* Fragments must not span 4k boundaries. */
EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
/* No limitations on boundary crossing */
EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
efsys_dma_addr_t, addr,

7
drivers/net/sfc/base/efx.h
View File

@ -1158,6 +1158,13 @@ typedef struct efx_nic_cfg_s {
uint32_t enc_rx_batch_max;
/* Number of rx descriptors the hardware requires for a push. */
uint32_t enc_rx_push_align;
/* Maximum amount of data in DMA descriptor */
uint32_t enc_tx_dma_desc_size_max;
/*
* Boundary which DMA descriptor data must not cross or 0 if no
* limitation.
*/
uint32_t enc_tx_dma_desc_boundary;
/*
* Maximum number of bytes into the packet the TCP header can start for
* the hardware to apply TSO packet edits.

16
drivers/net/sfc/base/efx_tx.c
View File

@ -745,8 +745,12 @@ siena_tx_qpost(
size_t size = ebp->eb_size;
efsys_dma_addr_t end = start + size;
/* Fragments must not span 4k boundaries. */
EFSYS_ASSERT(P2ROUNDUP(start + 1, 4096) >= end);
/*
* Fragments must not span 4k boundaries.
* Here it is a stricter requirement than the maximum length.
*/
EFSYS_ASSERT(P2ROUNDUP(start + 1,
etp->et_enp->en_nic_cfg.enc_tx_dma_desc_boundary) >= end);
EFX_TX_DESC(etp, start, size, ebp->eb_eop, added);
}
@ -1005,8 +1009,12 @@ siena_tx_qdesc_dma_create(
__in boolean_t eop,
__out efx_desc_t *edp)
{
/* Fragments must not span 4k boundaries. */
EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
/*
* Fragments must not span 4k boundaries.
* Here it is a stricter requirement than the maximum length.
*/
EFSYS_ASSERT(P2ROUNDUP(addr + 1,
etp->et_enp->en_nic_cfg.enc_tx_dma_desc_boundary) >= addr + size);
EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
efsys_dma_addr_t, addr,

4
drivers/net/sfc/base/hunt_nic.c
View File

@ -301,6 +301,10 @@ hunt_board_cfg(
/* Alignment for WPTR updates */
encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available

4
drivers/net/sfc/base/medford_nic.c
View File

@ -298,6 +298,10 @@ medford_board_cfg(
/* Alignment for WPTR updates */
encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
/* No boundary crossing limits */
encp->enc_tx_dma_desc_boundary = 0;
/*
* Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
* MC_CMD_GET_RESOURCE_LIMITS here as that reports the available

4
drivers/net/sfc/base/siena_nic.c
View File

@ -135,6 +135,10 @@ siena_board_cfg(
/* Alignment for WPTR updates */
encp->enc_rx_push_align = 1;
encp->enc_tx_dma_desc_size_max = EFX_MASK32(FSF_AZ_TX_KER_BYTE_COUNT);
/* Fragments must not span 4k boundaries. */
encp->enc_tx_dma_desc_boundary = 4096;
/* Resource limits */
rc = efx_mcdi_get_resource_limits(enp, &nevq, &nrxq, &ntxq);
if (rc != 0) {